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MCP3912 Datenblatt(PDF) 23 Page - Microchip Technology

Teilenummer MCP3912
Bauteilbeschribung  3V Four-Channel Analog Front End
PDF  82 Pages
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Hersteller  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP3912 Datenblatt(HTML) 23 Page - Microchip Technology

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 2014 Microchip Technology Inc.
DS20005348A-page 23
MCP3912
Since this is the output data rate, and because the
decimation filter is a SINC (or notch) filter, there is a
notch in the filter transfer function at each integer
multiple of this rate.
Table 4-2 describes the various combinations of OSR
and PRESCALE, and their associated AMCLK,
DMCLK and DRCLK rates.
TABLE 4-2:
DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE,
MCLK = 4 MHZ
PRE<1:0>
OSR<2:0>
OSR
AMCLK
DMCLK
DRCLK
DRCLK
(ksps)
SINAD
(dB)
Note 1
ENOB
from
SINAD
(bits)
Note 1
11
1
1
1
4096
MCLK/8
MCLK/32
MCLK/131072
.035
102.5
16.7
11
1
1
1
2048
MCLK/8
MCLK/32
MCLK/65536
.061
100
16.3
11
1
1
1
1024
MCLK/8
MCLK/32
MCLK/32768
.122
97
15.8
11
1
1
1
512
MCLK/8
MCLK/32
MCLK/16384
.244
96
15.6
11
0
1
1
256
MCLK/8
MCLK/32
MCLK/8192
0.488
94
15.3
11
0
1
0
128
MCLK/8
MCLK/32
MCLK/4096
0.976
90
14.7
11
0
0
1
64
MCLK/8
MCLK/32
MCLK/2048
1.95
83
13.5
11
0
0
0
32
MCLK/8
MCLK/32
MCLK/1024
3.9
70
11.3
10
1
1
1
4096
MCLK/4
MCLK/16
MCLK/65536
.061
102.5
16.7
10
1
1
1
2048
MCLK/4
MCLK/16
MCLK/32768
.122
100
16.3
10
1
1
1
1024
MCLK/4
MCLK/16
MCLK/16384
.244
97
15.8
10
1
1
1
512
MCLK/4
MCLK/16
MCLK/8192
.488
96
15.6
10
0
1
1
256
MCLK/4
MCLK/16
MCLK/4096
0.976
94
15.3
10
0
1
0
128
MCLK/4
MCLK/16
MCLK/2048
1.95
90
14.7
10
0
0
1
64
MCLK/4
MCLK/16
MCLK/1024
3.9
83
13.5
10
0
0
0
32
MCLK/4
MCLK/16
MCLK/512
7.8125
70
11.3
01
1
1
1
4096
MCLK/2
MCLK/8
MCLK/32768
.122
102.5
16.7
01
1
1
1
2048
MCLK/2
MCLK/8
MCLK/16384
.244
100
16.3
01
1
1
1
1024
MCLK/2
MCLK/8
MCLK/8192
.488
97
15.8
01
1
1
1
512
MCLK/2
MCLK/8
MCLK/4096
.976
96
15.6
01
0
1
1
256
MCLK/2
MCLK/8
MCLK/2048
1.95
94
15.3
01
0
1
0
128
MCLK/2
MCLK/8
MCLK/1024
3.9
90
14.7
01
0
0
1
64
MCLK/2
MCLK/8
MCLK/512
7.8125
83
13.5
01
0
0
0
32
MCLK/2
MCLK/8
MCLK/256
15.625
70
11.3
00
1
1
1
4096
MCLK
MCLK/4
MCLK/16384
.244
102.5
16.7
00
1
1
0
2048
MCLK
MCLK/4
MCLK/8192
.488
100
16.3
00
1
0
1
1024
MCLK
MCLK/4
MCLK/4096
.976
97
15.8
00
1
0
0
512
MCLK
MCLK/4
MCLK/2048
1.95
96
15.6
00
0
1
1
256
MCLK
MCLK/4
MCLK/1024
3.9
94
15.3
00
0
1
0
128
MCLK
MCLK/4
MCLK/512
7.8125
90
14.7
00
0
0
1
64
MCLK
MCLK/4
MCLK/256
15.625
83
13.5
00
0
0
0
32
MCLK
MCLK/4
MCLK/128
31.25
70
11.3
Note 1:
For OSR = 32 and 64, DITHER = None. For OSR = 128 and higher, DITHER = Maximum. The SINAD
values are given from GAIN = 1.



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