MCP3912 datasheet(19/82 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005348A-page 19

MCP3912

3.1

Analog Power Supply (AVDD)

AVDD is the power supply voltage for the analog

circuitry within the MCP3912. It is distributed on several

pins (pins 11 and 25 in the QFN-28 package, one pin

only in

the

SSOP-28

package). For optimal

performance, connect these pins together using a star

connection, and connect the appropriate bypass

capacitors (typically a 10 µF in parallel with a 0.1 µF

ceramic). AVDD should be maintained between 2.7V

and 3.6V for specified operation.

To ensure proper functionality of the device, at least

one of these pins must be properly connected. To

ensure optimal performance of the device, all the pins

must be properly connected. If any of these pins are left

floating, the accuracy and noise specifications are not

ensured.

3.2

ADC Differential Analog Inputs

(CHn+/CHn-)

The CHn+/- pins (n comprised between 0 and 3) are

the four fully-differential analog voltage inputs for the

delta-sigma ADCs.

The linear and specified region of the channels is

dependent on the PGA gain. This region corresponds

to a differential voltage range of ±600 mV/GAIN with

VREF = 1.2V.

The maximum absolute voltage, with respect to AGND,

for each CHn+/- input pin is ±1V with no distortion, and

±2V with no breaking after continuous voltage. This

maximum absolute voltage is not proportional to the

VREF voltage.

3.3

Noninverting Reference Input,

Internal Reference Output

(REFIN+/OUT)

This pin is the noninverting side of the differential

voltage reference input for all ADCs or the internal

voltage reference output.

When VREFEXT = 1, an external voltage reference

source can be used, and the internal voltage reference

is disabled. When using an external differential voltage

reference, it should be connected to its VREF+ pin.

When using an external single-ended reference, it

should be connected to this pin.

When VREFEXT = 0, the internal voltage reference is

enabled and connected to this pin through a switch.

This voltage reference has minimal drive capability and

thus needs proper buffering and bypass capacitances

(a 0.1 µF ceramic capacitor is sufficient in most cases)

if used as a voltage source.

If the voltage reference is only used as an internal

VREF, adding bypass capacitance on REFIN+/OUT is

not necessary for keeping ADC accuracy, but a minimal

0.1 µF ceramic capacitance can be connected to avoid

EMI/EMC susceptibility issues due to the antenna

created by the REFIN+/OUT pin if left floating.

3.4

Inverting Reference Input (REFIN-)

This pin is the inverting side of the differential voltage

reference input for all ADCs. When using an external

differential voltage reference, it should be connected to

its VREF- pin. When using an external single-ended

voltage reference, or when VREFEXT = 0 (default) and

using the internal voltage reference, the pin should be

directly connected to AGND.

3.5

Analog Ground (AGND)

AGND is the ground reference voltage for the analog

circuitry within the MCP3912. It is distributed on several

pins (pins 10 and 26 in the QFN-28 package, one pin

only in the

SSOP-28 package). For

optimal

performance, it is recommended to connect these pins

together using a star connection, and to connect it to

the same ground node voltage as DGND with a star

connection.

At least one of these pins needs to be properly

connected to ensure proper functionality of the device.

All of these pins need to be properly connected to

ensure optimal performance of the device. If any of

these pins are left floating, the accuracy and noise

specifications are not ensured. If an analog ground

plane is available, it is recommended that these pins be

tied to this plane of the PCB. This plane should also

reference all other analog circuitry in the system.

3.6

Digital Ground (DGND)

DGND is the ground reference voltage for the digital

circuitry within the MCP3912. It is distributed on several

pins (pins 13, 15 and 23 in the QFN-28 package, two

pins only in the SSOP-28 package). For optimal

performance, connect these pins together using a star

connection and connect it to the same ground node

voltage as AGND with a star connection.

At least one of these pins needs to be properly

connected to ensure proper functionality of the device.

All of these pins need to be properly connected to

ensure optimal performance of the device. If any of

these pins are left floating, the accuracy and noise

specifications are not ensured. If a digital ground plane

is available, it is recommended that these pins be tied

to this plane of the Printed Circuit Board (PCB). This

plane should also reference all other digital circuitry in

the system.

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