MCP3912 datasheet(28/82 Pages) MICROCHIP

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MCP3912

DS20005348A-page 28

 2014 Microchip Technology Inc.

When an ADC exits ADC Shutdown mode, any phase

delay present before shutdown was entered will still be

present. If one ADC was not in Shutdown, the ADC

leaving Shutdown mode will automatically resynchro-

nize the phase delay relative to the other ADC channel

per the phase delay register block and give data ready

pulses accordingly.

If an ADC is placed in Shutdown mode while others are

converting, it does not shut down the internal clock.

When coming back out of Shutdown mode, it will

automatically be resynchronized with the clock that did

not stop during reset.

If all ADCs are in ADC Shutdown mode, the clock is not

distributed to the input structure or to the digital core for

low-power operation. This can potentially cause high

analog input leakage currents at the analog inputs if the

input voltage is highly negative (typically below -0.6V

referred to AGND). Once either of the ADCs is back to

normal operation, the clock is automatically distributed

again.

4.22

Full Shutdown Mode

The lowest power consumption can be achieved when

SHUTDOWN<3:0> = 1111,

VREFEXT = CLKEXT = 1. This mode is called Full

Shutdown mode, and no analog circuitry is enabled. In

this mode, both AVDD and DVDD POR monitoring are

also disabled and no clock is propagated throughout

the chip. All ADCs are in Shutdown mode, and the

internal voltage reference is disabled. This mode does

not reset the writable part of the register map to its

default values.

The clock is no longer distributed to the input structure as

well. This can potentially cause high analog input leak-

age currents at the analog inputs if the input voltage is

highly negative (typically below -0.6V referred to AGND).

The only circuit that remains active is the SPI interface,

but this circuit does not induce any static power

consumption. If SCK is idle, the only current

consumption comes from the leakage currents induced

by the transistors.

This mode can be used to power-down the chip

completely and avoid power consumption when there

is no data to convert at the analog inputs. Any SCK or

MCLK edge occurring while in this mode will induce

dynamic power consumption.

Once any of the SHUTDOWN<3:0>, CLKEXT and

VREFEXT bits return to ‘0’, the two POR monitoring

blocks are operational and AVDD and DVDD monitoring

can take place.

4.23

Measurement Error

The measurement error specification is typically used

in power meter applications. This specification is a

measurement of the linearity of the active energy of a

given power meter across its dynamic range.

For this measurement, the goal is to measure the

active energy of one phase when the voltage Root

Mean Square (RMS) value is fixed and the current

RMS value is sweeping across the dynamic range

specified by the meter. The measurement error is the

nonlinearity error of the energy power across the

current dynamic range. It is expressed as a

percentage. Equation 4-13 shows the formula that

calculates the measurement error:

EQUATION 4-13:

In the present device, the calculation of the active energy

is done externally as a post-processing step that typically

happens in the microcontroller, considering, for example,

the even channels as current channels and the odd

channels as voltage channels. The odd channels

(voltages) are fed with a full-scale sine wave at 600 mV

peak,

and

are

configured

with

GAIN = 1

and

DITHER = Maximum. To obtain the active energy

measurement error graphs, the even channels are fed

with sine waves with amplitudes that vary from 600 mV

peak to 60 µV peak, representing a 10000:1 dynamic

range. The offset is removed on both current and voltage

channels, and the channels are multiplied together to give

instantaneous power. The active energy is calculated by

multiplying the current and voltage channel, and

averaging the results of this power during 20 seconds to

extract the active energy. The sampling frequency is

chosen as a multiple integer of line frequency (coherent

sampling). Therefore, the calculation does not take into

account any residue coming from bad synchronization.

The measurement error is a function of IRMS and varies

with the OSR, averaging time and MCLK frequency,

and is tightly coupled with the noise and linearity

specifications. The measurement error is a function of

the linearity and THD of the ADCs, while the standard

deviation of the measurement error is a function of the

noise specification of the ADCs. Overall, the low THD

specification enables low measurement error on a very

large dynamic range (e.g. 10,000:1). A low noise and

high SNR specification enables the decreasing of the

measurement time and, therefore, the calibration time,

to obtain a reliable measurement error specification.

Figure 2-5 shows the typical measurement error curves

obtained with the samples acquired by the MCP3912,

using the default settings with a 1-point and 2-point cal-

ibration. These calibrations are detailed in Section 7.0

“Basic Application Recommendations”

Measurement Error I

RMS

 Measured Active Energy Active Energy present at inputs

–

Active Energy present at inputs

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