MCP3912 datasheet(62/82 Pages) MICROCHIP

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MCP3912

DS20005348A-page 62

 2014 Microchip Technology Inc.

8.3

PHASE Register – Phase

Configuration Register for

Channel Pairs 2/3 and 0/1

Any write to this register automatically resets and

restarts all active ADCs.

Name

Bits

Address

Cof.

PHASE

0x0A

R/W

PHASE REGISTER

R/W-0

PHASEB<11>

PHASEB<10>

PHASEB<9>

PHASEB<8>

PHASEB<7>

PHASEB<6>

PHASEB<5>

PHASEB<4>

bit 23

bit 16

R/W-0

PHASEB<3>

PHASEB<2>

PHASEB<1>

PHASEB<0>

PHASEA<11>

PHASEA<10>

PHASEA<9>

PHASEA<8>

bit 15

bit 8

R/W-0

PHASEA<7>

PHASEA<6>

PHASEA<5>

PHASEA<4>

PHASEA<3>

PHASEA<2>

PHASEA<1>

PHASEA<0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 23-12

PHASEB<11:0>

Phase delay between channels CH2 and CH3 (reference). Delay = PHASEB<11:0>

decimal code/DMCLK

bit 11-0

PHASEA<11:0>

Phase delay between channels CH0 and CH1(reference). Delay = PHASEA<11:0>

decimal code/DMCLK

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