MCP3912 datasheet(39/82 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005348A-page 39

MCP3912

5.10

Data Ready Link

There are two modes defined with the DR_LINK bit in

the STATUSCOM register that control the data ready

pulses. The position of the data ready pulses varies

with respect to this mode, to the OSR<2:0> and to the

PHASE register settings. Section 5.11 “Data Ready

Status Bits”

represents the behavior of the Data

Ready pin with the two DR_LINK configurations

• DR_LINK = 0: Data ready pulses from all enabled

channels are output on the DR pin.

• DR_LINK = 1 (Recommended and Default mode):

Only the data ready pulses from the most lagging

ADC between all the active ADCs are present on

the DR pin.

The lagging ADC data ready position depends on the

PHASE register, the PRE<1:0> and the OSR<2:0>

settings. In this mode, the active ADCs are linked

together, so their data is latched together when the

lagging ADC output is ready. For power metering

applications, DR_LINK = 1 is recommended (Default

mode); it allows the host MCU to gather all channels

synchronously within a unique interrupt pulse, and it

ensures that all channels have been latched at the

same time so that no data corruption is happening.

5.11

Data Ready Status Bits

In addition to the data ready pin indicator, the

MCP3912 device includes a separate data ready status

bit for each channel. Each ADC channel CHn is

associated to the corresponding DRSTATUS<n> that

can be read at all times in the STATUSCOM register.

These status bits can be used to synchronize the data

retrieval in case the DR pin is not connected (see

Section 6.8

“ADC

Channels

Latching

and

Synchronization”

The DRSTATUS<3:0> bits are not writable; writing on

them has no effect. They have a default value of '1',

which indicates that the data of the corresponding ADC

is not ready. This means that the ADC output register

has not been updated since the last reading (or since

the last reset). The DRSTATUS bits take the '0' state,

once the ADC channel register is updated (which hap-

pens at a DRCLK rate). A simple read of the STATUS-

COM register clears all the DRSTATUS bits to their

default value ('1').

In the case of DR_LINK = 1, the DRSTATUS<3:0> bits

are all updated synchronously with the most lagging

channel at the same time the DR pulse is generated. In

case of DR_LINK = 0, each DRSTATUS bit is updated

independently

and

synchronously

with

its

corresponding channel.

5.12

Crystal Oscillator

The MCP3912 includes a Pierce-type crystal oscillator

with very high stability and ensures very low tempco

and jitter for the clock generation. This oscillator can

handle crystal frequencies up to 20 MHz, provided

proper load capacitances and quartz quality factors are

used. The crystal oscillator is enabled when

CLKEXT = 0 in the CONFIG1 register.

For a proper start-up, the load capacitors of the crystal

should be connected between OSC1 and DGND and

between OSC2 and DGND. They should also respect

Equation 5-7.

EQUATION 5-7:

When CLKEXT = 1, the crystal oscillator is bypassed

by a digital buffer to allow direct clock input for an

external clock (see Figure 4-1). In this case, the OSC2

pin is pulled down internally to DGND and should be

connected to DGND externally for better EMI/EMC

immunity.

TABLE 5-9:

PHASE VALUES WITH

MCLK = 4 MHZ, OSR = 4096,

PRE<1:0> = 00

PHASEX<11:0> for

the Channel Pair

CH<n/n+1>

Hex

Delay

(CH<n> relative

to CH<n+1>)

0111 111111 11

0x7FF

+ 2047 µs

0111 111111 10

0x7FE

+ 2046 µs

0000 000000 01

0x001

+ 1 µs

0000 000000 00

0x000

0 µs

1111 111111 11

0xFFF

- 1 µs

1000 000000 01

0x801

- 2047 µs

1000 000000 00

0x800

-2048 µs

1.6





LOAD

------------------------







Where:

f = crystal frequency in MHz

CLOAD = load capacitance in pF including

parasitics from the PCB

RM = motional resistance in ohms of the

quartz

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