MCP3912 datasheet(27/82 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005348A-page 27

MCP3912

EQUATION 4-12:

Where: VCM = (CHn+ + CHn-)/2 is the common-mode

input voltage, and VOUT is the equivalent input voltage

that the output code translates to, with the ADC transfer

function.

In the MCP3912 specification, VCM varies from -1V to

+1V.

4.19

ADC Reset Mode

ADC Reset mode (also called Soft Reset mode) can

only be entered through setting the RESET<3:0> bits

high in the Configuration register. This mode is defined

as the condition where the converters are active, but

their output is forced to 0.

The Flash ADC output of the corresponding channel

will be reset to its default value (0011) in the MOD

The ADCs can immediately output meaningful codes

after leaving Reset mode (and after the sinc filter

settling time). This mode is both entered and exited

through bit settings in the Configuration register.

Each converter can be placed in Soft Reset mode

independently. The Configuration registers are not

modified by the Soft Reset mode. A data ready pulse

will not be generated by an ADC channel in Reset

mode.

When an ADC exits ADC Reset mode, any phase delay

present before Reset was entered will still be present.

If one ADC was not in Reset, the ADC leaving Reset

mode will automatically resynchronize the phase delay

relative to the other ADC channel per the phase delay

If an ADC is placed in Reset mode while others are

converting, it does not shut down the internal clock.

When coming out of reset, it will be automatically

resynchronized with the clock, which did not stop

during Reset.

If all ADCs are in Soft Reset mode, the clock is no

longer distributed to the digital core for low-power

operation. Once any of the ADCs are back to normal

operation, the clock is automatically distributed again.

However, when the four channels are in Soft Reset

mode, the input structure is still clocking if MCLK is

applied in order to properly bias the inputs so that no

leakage current is observed. If MCLK is not applied,

large analog input leakage currents can be observed

for highly negative input voltages (typically below -0.6V

referred to AGND).

4.20

Hard Reset Mode (RESET = 0)

This mode is only available during a POR or when the

RESET pin is pulled logic low. The RESET pin logic-low

state places the device in Hard Reset mode. In this

mode, all internal registers are reset to their default

state.

The DC biases for the analog blocks are still active, i.e.,

the MCP3912 is ready to convert. However, this pin

clears all conversion data in the ADCs. The

comparators’ outputs of all ADCs are forced to their

Reset state (0011). The SINC filters are all reset, as

well as their double output buffers. The Hard Reset

mode requires a minimum pulse low time (see

Section 1.0 “Electrical Characteristics”

). During a

Hard Reset, no communication with the part is

possible. The digital interface is maintained in a Reset

state.

During this state, the clock MCLK can be applied to the

part in order to properly bias the input structures of all

channels. If not applied, large analog input leakage

currents can be observed for highly negative input

signals and, after removing the Hard Reset state, a

certain start-up time is necessary to bias the input

structure properly. During this delay, the ADC

conversions can be inaccurate.

4.21

ADC Shutdown Mode

ADC Shutdown mode is defined as a state where the

converters and their biases are off, consuming only

leakage current. When one of the SHUTDOWN<3:0>

bits is reset to ‘0’, the analog biases of the

corresponding channel will be enabled, as well as the

clock and the digital circuitry. The ADC of the

corresponding channel will give a data ready after the

SINC filter settling time has occurred. However, since

the analog biases are not completely settled at the

beginning of the conversion, the sampling may not be

accurate during about 1 ms (corresponding to the

settling time of the biasing in worst-case conditions). In

order to ensure accuracy, the data ready pulse within

the delay of 1 ms + settling time of the SINC filter

should be discarded.

Each converter can be placed in Shutdown mode

independently. The configuration registers are not

modified by the Shutdown mode. This mode is only

available through programming the SHUTDOWN<3:0>

bits of the CONFIG1 register.

The output data is flushed to all zeros while in ADC

Shutdown mode. No data ready pulses are generated

by any ADC while in ADC Shutdown mode.

CMRR dB



V

OUT

V

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