| Datenblatt-Suchmaschine für elektronische Bauteile |
|
MCP3912 Datenblatt(PDF) 33 Page - Microchip Technology |
|
|
|||||||||||||||||||||||||||||
MCP3912 Datenblatt(HTML) 33 Page - Microchip Technology |
|
33 / 82 page ![]() 2014 Microchip Technology Inc. DS20005348A-page 33 MCP3912 The gain of the transfer function of this filter is one at each multiple of DMCLK (typically 1 MHz), so a proper anti-aliasing filter must be placed at the inputs. This will attenuate the frequency content around DMCLK and keep the desired accuracy over the baseband of the converter. This anti-aliasing filter can be a simple, first- order RC network, with a sufficiently low time constant to generate high rejection at the DMCLK frequency . Any unsettled data is automatically discarded to avoid data corruption. Each data ready pulse corresponds to fully settled data at the output of the decimation filter. The first data available at the output of the decimation filter is present after the complete settling time of the filter (see Table 5-3). After the first data has been processed, the delay between two data ready pulses coming from the same ADC channel is one DRCLK period. The data stream from input to output is delayed by an amount equal to the settling time of the filter (which is the group delay of the filter). The achievable resolution, the -3 dB bandwidth and the settling time at the output of the decimation filter (the output of the ADC), is dependent on the OSR of each sinc filter and is summarized in Table 5-3. FIGURE 5-3: SINC Filter Frequency Response, OSR = 256, MCLK = 4 MHz, PRE<1:0> = 00. FIGURE 5-4: SINC Filter Frequency Response, OSR = 4096 (in pink), OSR = 512 (in blue), MCLK = 4 MHz, PRE<1:0> = 00. TABLE 5-3: OVERSAMPLING RATIO AND SINC FILTER SETTLING TIME OSR<2:0> OSR3 OSR1 Total OSR Resolution in Bits (No Missing Code) Settling Time -3 dB Bandwidth 000 32 1 32 17 96/DMCLK 0.26*DRCLK 001 64 1 64 20 192/DMCLK 0.26*DRCLK 010 128 1 128 23 384/DMCLK 0.26*DRCLK 011 256 1 256 24 768/DMCLK 0.26*DRCLK 100 512 1 512 24 1536/DMCLK 0.26*DRCLK 101 512 2 1024 24 2048/DMCLK 0.37*DRCLK 110 512 4 2048 24 3072/DMCLK 0.42*DRCLK 111 512 8 4096 24 5120/DMCLK 0.43*DRCLK -80 -60 -40 -20 0 -120 -100 1 10 100 1000 10000 100000 Input Frequency (Hz) -100 -80 -60 -40 -20 0 -160 -140 -120 1 100 10000 1000000 Input Frequency (Hz) |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |