MCP3912 datasheet(37/82 Pages) MICROCHIP

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 2014 Microchip Technology Inc.

DS20005348A-page 37

MCP3912

5.7

Power-on Reset

The MCP3912 contains an internal POR circuit that

monitors both analog and digital supply voltages during

operation. The typical threshold for a power-up event

detection is 2.0V ±10% and a typical start-up time

(tPOR) of 50 µs. The POR circuit has a built-in hystere-

sis for improved transient spike immunity that has a

typical value of 200 mV. Proper decoupling capacitors

(0.1 µF in parallel with 10 µF) should be mounted as

close as possible to the AVDD and DVDD pins, providing

additional transient immunity.

Figure 5-7 illustrates the different conditions at a

power-up and a power-down event in typical

conditions. All internal DC biases are not settled until at

least 1 ms in worst case conditions after system POR.

Any data-ready pulse occurring within 1 ms plus the

SINC filter settling time after system reset should be

ignored to ensure proper accuracy. After POR, data

ready pulses are present at the pin with all the default

conditions in the Configuration registers.

Both AVDD and DVDD are monitored, so either power

supply can sequence first.

FIGURE 5-7:

Power-On Reset Operation.

5.8

Hard Reset Effect On Delta-Sigma

Modulator/SINC Filter

When the RESET pin is logic low, all ADCs will be in

Reset and output code 0x000000h. The RESET pin

performs a hard reset (DC biases are still on, the part

is ready to convert) and clears all charges contained in

the delta-sigma modulators. The comparator’s output is

‘0011’ for each ADC.

The SINC filters are all reset, as well as their double

output buffers. This pin is independent of the serial

interface. It brings all the registers to the default state.

When RESET is logic low, any write with the SPI

interface will be disabled and will have no effect. All

output pins (SDO, DR) are high-impedance.

If an external clock (MCLK) is applied, the input struc-

ture is enabled and is properly biasing the substrate of

the input transistors. In this case, the leakage current

on the analog inputs is low if the analog input voltages

are kept between -1V and +1V.

If MCLK is not applied when in Reset mode, the

leakage can be high if the analog inputs are

below -0.6V, as referred to AGND.

5.9

Phase Delay Block

The MCP3912 incorporates a phase delay generator

which ensures that each pair of ADCs (CH0/1, CH2/3)

are converting the inputs with a fixed delay between

them. The four ADCs are synchronously sampling, but

the averaging of modulator outputs is delayed so that

the SINC filter outputs (thus the ADC outputs) show a

fixed phase delay as determined by the PHASE

reference channels for the phase delays of each pair,

and set the time reference. Typically, these channels

can be the voltage channels for a polyphase energy

metering application. These odd channels are

synchronous at all times, so they become ready and

output a data ready pulse at the same time. The even

channels (CH0/2) are delayed, compared to the time

reference (CH1/3), by a fixed amount of time defined

for each pair channel in the PHASE register.

POR

State

Power-Up

Normal

POR

State

Biases are

unsettled.

Conversions

started here may

not be accurate

Biases are settled.

Conversions started

here are accurate.

Analog biases

settling time

SINC filter

settling

time

Voltage

(AVDD, DVDD)

Time

POR Threshold

up (2.0V typical)

(1.8V typical)

tPOR

Operation

Any data-read pulse occurring

during this time can yield

inaccurate output data. It is

recommended to discard them.

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