MCP3912 datasheet(70/82 Pages) MICROCHIP

70 / 82 page

MCP3912

DS20005348A-page 70

 2014 Microchip Technology Inc.

8.9

SECURITY Register – Password

and CRC-16 On Register Map

GAINCAL_CHN REGISTERS

R/W-0

GAINCAL_CHn<23:0>

bit 23

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 23-0

GAINCAL_CHn:

Digital gain error calibration value for the corresponding channel CHn. This register

is 24-bit signed MSB first coding with a range of -1x to +0.9999999x (from 0x800000 to 0x7FFFFF).

The gain calibration adds 1x to this register and multiplies it to the output code of the channel bit-by-bit,

after offset calibration. The range of the gain calibration is thus from 0x to 1.9999999x (from 0x800000

to 0x7FFFFF). The LSB corresponds to a 2-23 increment in the multiplier. CHn Output

Code = (GAINCAL_CHn+1)*ADC CHn Output Code. This register is a Don't Care if EN_GAINCAL = 0

(Gain calibration disabled) but its value is not cleared by the EN_GAINCAL bit.

Name

Bits

Address

Cof.

LOCK/CRC

0x1F

R/W

LOCK/CRC REGISTER

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

R/W-0

R/W-1

LOCK<7>

LOCK<6>

LOCK<5>

LOCK<4>

LOCK<3>

LOCK<2>

LOCK<1>

LOCK<0>

bit 23

bit 16

R-0

CRCREG<15>

CRCREG<14>

CRCREG<13>

CRCREG<12>

CRCREG<11>

CRCREG<10>

CRCREG<9>

CRCREG<8>

bit 15

bit 8

R-0

CRCREG<7>

CRCREG<6>

CRCREG<5>

CRCREG<4>

CRCREG<3>

CRCREG<2>

CRCREG<1>

CRCREG<0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 23-16

LOCK<7:0>:

Lock Code for the writable part of the register map

LOCK<7:0> = PASSWORD =0xA5 (Default value): The entire register map is writable. The CRCREG<15:0> bits

and the CRC Interrupt are cleared. No CRC-16 checksum on register map is calculated.

LOCK<7:0> are different than 0xA5: The only writable register is the LOCK/CRC register. All other registers will

appear as undefined while in this mode. The CRCREG checksum is calculated continuously and can generate

interrupts if the CRC Interrupt EN_INT bit has been enabled. If a write to a register needs to be performed, the

user needs to unlock the register map beforehand by writing 0xA5 to the LOCK<7:0> bits.

bit 15-0

CRCREG<15:0>:

CRC-16 Checksum that is calculated with the writable part of the register map as a message. This

is a read-only 16-bit code. This checksum is continuously recalculated and updated every 16 DMCLK periods.

It is reset to its default value (0x0000) when LOCK<7:0> = 0xA5.

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