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MCP3912 Datenblatt(PDF) 24 Page - Microchip Technology

Teilenummer MCP3912
Bauteilbeschribung  3V Four-Channel Analog Front End
PDF  82 Pages
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Hersteller  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

MCP3912 Datenblatt(HTML) 24 Page - Microchip Technology

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MCP3912
DS20005348A-page 24
 2014 Microchip Technology Inc.
4.5
OSR – Oversampling Ratio
This is the ratio of the sampling frequency to the output
data rate; OSR = DMCLK/DRCLK. The default
OSR<2:0>
is
256,
or
with
MCLK = 4 MHz,
PRESCALE = 1, AMCLK = 4 MHz, fS = 1 MHz and
fD = 3.90625 ksps. The OSR<2:0> bits in Table 4-3 in
the CONFIG0 register are used to change the
oversampling ratio (OSR).
4.6
Offset Error
This is the error induced by the ADC when the inputs
are shorted together (VIN = 0V). The specification
incorporates both PGA and ADC offset contributions.
This error varies with PGA and OSR settings. The
offset is different on each channel and varies from chip-
to-chip. The offset is specified in µV. The offset error
can be digitally compensated independently on each
channel through the OFFCAL_CHn registers with a
24-bit calibration word.
The offset on the MCP3912 has a low-temperature
coefficient.
4.7
Gain Error
This is the error induced by the ADC on the slope of the
transfer function. It is the deviation expressed in a per-
centage, compared to the ideal transfer function
defined in Equation 5-3. The specification incorporates
both PGA and ADC gain error contributions, but not the
VREF contribution (it is measured with an external
VREF).
This error varies with PGA and OSR settings. The gain
error can be digitally compensated independently on
each channel through the GAINCAL_CHn registers
with a 24-bit calibration word.
The gain error on the MCP3912 has a low temperature
coefficient.
4.8
Integral Nonlinearity Error
Integral nonlinearity error is the maximum deviation of
an ADC transition point from the corresponding point of
an ideal transfer function, with the offset and gain
errors removed or with the end points equal to zero.
It is the maximum remaining error after calibration of
offset and gain errors for a DC input signal.
4.9
Signal-to-Noise Ratio (SNR)
For the MCP3912 ADCs, the signal-to-noise ratio is a
ratio of the output fundamental signal power to the
noise power (not including the harmonics of the signal)
when the input is a sine wave at a predetermined
frequency (see Equation 4-4). It is measured in dB.
Usually, only the maximum signal-to-noise ratio is
specified. The SNR figure depends mainly on the OSR
and DITHER settings of the device.
EQUATION 4-4:
SIGNAL-TO-NOISE RATIO
4.10
Signal-To-Noise Ratio And
Distortion (SINAD)
The most important Figure of Merit for analog
performance of the ADCs present on the MCP3912 is
the
Signal-to-Noise
And
Distortion
(SINAD)
specification.
The Signal-to-Noise And Distortion ratio is similar to
signal-to-noise ratio, with the exception that you must
include the harmonic’s power in the noise power
calculation
(see
Equation 4-5).
The
SINAD
specification depends mainly on the OSR and DITHER
settings.
EQUATION 4-5:
SINAD EQUATION
The calculated combination of SNR and THD per the
following formula also yields SINAD (see Equation 4-6).
EQUATION 4-6:
SINAD, THD AND SNR
RELATIONSHIP
TABLE 4-3:
MCP3912 OVERSAMPLING
RATIO SETTINGS
OSR<2:0>
Oversampling Ratio
OSR
000
32
001
64
010
128
011
256 (Default)
100
512
101
1024
110
2048
111
4096
SNR dB

10
SignalPower
NoisePower
----------------------------------


log
=
SINAD dB

10
SignalPower
Noise
HarmonicsPower
+
---------------------------------------------------------------------


log
=
SINAD dB

10
10
SNR
10
-----------


10
THD
10
----------------


+
log
=



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