MCP3912 datasheet(36/82 Pages) MICROCHIP

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MCP3912

DS20005348A-page 36

 2014 Microchip Technology Inc.

5.6

Voltage Reference

5.6.1

INTERNAL VOLTAGE REFERENCE

The MCP3912 contains an internal voltage reference

source specially designed to minimize drift over

temperature. In order to enable the internal voltage

reference, the VREFEXT bit in the Configuration

VREF supplies reference voltage to all channels. The

typical value of this voltage reference is 1.2V ±2%. The

internal reference has a very low typical temperature

coefficient of ±9 ppm/°C, allowing the output to have

minimal variation with respect to temperature, since

they are proportional to (1/VREF).

The noise of the internal voltage reference is low

enough not to significantly degrade the SNR of the

ADC, if compared to a precision external low-noise

voltage reference. The output pin for the internal volt-

age reference is REFIN+/OUT.

If the voltage reference is only used as an internal

VREF, adding bypass capacitance on REFIN+/OUT is

not necessary for keeping ADC accuracy, but a minimal

0.1 µF ceramic capacitance can be connected to avoid

EMI/EMC susceptibility issues due to the antenna

created by the REFIN+/OUT pin, if left floating.

The bypass capacitors also help applications where the

voltage reference output is connected to other circuits.

In this case, additional buffering may be needed since

the output drive capability of this output is low.

Adding too much capacitance on the REFIN+/OUT pin

may slightly degrade the THD performance of the ADCs.

5.6.2

DIFFERENTIAL EXTERNAL

VOLTAGE INPUTS

When the VREFEXT bit is set to ‘1’, the two reference

pins (REFIN+/OUT, REFIN-) become a differential

voltage

reference

input.

The

voltage

the

REFIN+/OUT is noted VREF+, and the voltage at the

REFIN- pin is noted VREF-. The differential voltage

input value is shown in Equation 5-4.

EQUATION 5-4:

The specified VREF range is from 1.1V to 1.3V. The

REFIN- pin voltage (VREF-) should be limited to ±0.1V,

with respect to AGND. Typically, for single-ended

reference applications, the REFIN- pin should be

directly connected to AGND, with its own separate track

to avoid any spike due to switching noise.

These buffers are injecting a certain quantity of

1/f noise into the system. This noise can be modulated

with the incoming input signals and can limit the SNR

at very high OSR (OSR>256). To overcome this

limitation, these buffers include an auto-zeroing

algorithm that greatly diminishes their 1/f noise as well

as their offset, so that the SNR of the system is not

limited by this noise component, even at maximum

OSR. This auto-zeroing algorithm is performed

synchronously with the MCLK coming to the device.

5.6.3

TEMPERATURE COMPENSATION

(VREFCAL<7:0>)

The internal voltage reference consists of a proprietary

circuit and algorithm to compensate first-order and sec-

ond-order temperature coefficients (tempco). The com-

pensation enables very low temperature coefficients

(typically 9 ppm/°C) on the entire range of tempera-

tures, from

-40°C to +125°C. This temperature coef-

ficient varies from part to part.

This temperature coefficient can be adjusted on each

part through the VREFCAL<7:0> bits present in the

CONFIG0 register (bits 7 to 0). These register settings

are only for advanced users. VREFCAL<7:0> should

not be modified unless the user wants to calibrate the

temperature coefficient of the whole system or

application. The default value of this register is set to

0x50. The default value (0x50) was chosen to optimize

the standard deviation of the tempco across process

variation. The value can be slightly improved to around

7 ppm/°C if the VREFCAL<7:0> is written at 0x42, but

this setting degrades the standard deviation of the

VREF tempco.The typical variation of the temperature

coefficient of the internal voltage reference with respect

to the VREFCAL register code is shown in Figure 5-6.

Modifying the value stored in the VREFCAL<7:0> bits

may also vary the voltage reference in addition to the

temperature coefficient.

FIGURE 5-6:

VREF Tempco vs. VREFCAL

Trim Code Chart.

5.6.4

VOLTAGE REFERENCE BUFFERS

Each channel includes a voltage reference buffer tied

to the REFIN+/OUT pin, which allows the internal

capacitors to properly charge with the voltage

reference signals, even in the case of an external

voltage reference connection with weak load regulation

specifications. This ensures the correct amount of

current is sourced to each channel to guarantee their

accuracy specifications, and diminishes the constraints

on the voltage reference load regulation.

VREF =VREF+– VREF-

128

192

256

VREFCAL Register Trim Code (decimal)

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