CC1020-RTR1 datasheet(31/91 Pages) TI

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CC1020

SWRS046

Page 31 of 92

The DEC_DIV[4:0] bits in the FILTER

bandwidth. The 6 dB bandwidth is given

by:

ChBW = 307.2 / (DEC_DIV + 1) [kHz]

where the IF frequency is set to 307.2

kHz.

In SmartRF® Studio the user specifies the

channel spacing and the channel filter

bandwidth is set according to Table 18.

For narrowband systems with channel

spacings of 12.5 and 25 kHz the channel

filter bandwidth is 12.288 kHz and 19.2

kHz respectively to comply with ARIB STD

T-67 and EN 300 220.

For wideband systems (channel spacing of

50 kHz and above) it is possible to use

different channel filter bandwidths than

given in Table 18.

There is a trade-off between selectivity as

well as sensitivity and accepted frequency

tolerance. In applications where larger

frequency drift is expected, the filter

bandwidth can be increased, but with

reduced adjacent channel rejection (ACR)

and sensitivity.

Channel

spacing

[kHz]

Filter

bandwidth

[kHz]

FILTER.DEC_DIV

[4:0]

[decimal(binary)]

12.5

12.288

24 (11000b)

19.2

15 (01111b)

25.6

11 (01011b)

100

51.2

5 (00101b)

150

102.4

2 (00010b)

200

153.6

1 (00001b)

500

307.2

0 (00000b)

Table 18. Channel filter bandwidths used

for the channel spacings defined in

SmartRF® Studio

12.3. Demodulator, Bit Synchronizer and Data Decision

The block diagram for the demodulator,

data slicer and bit synchronizer is shown

in Figure 13. The built-in bit synchronizer

synchronizes the internal clock to the

incoming

data

and

performs

data

decoding. The data decision is done using

over-sampling and digital filtering of the

incoming

signal.

This

improves

the

reliability of the data transmission. Using

the synchronous modes simplifies the

data-decoding task substantially.

The

recommended

preamble

‘010101…’ bit pattern. The same bit

pattern should also be used in Manchester

mode, giving a ‘011001100110…‘chip’

pattern. This is necessary for the bit

synchronizer to synchronize to the coding

correctly.

The data slicer does the bit decision.

Ideally the two received FSK frequencies

are placed symmetrically around the IF

frequency. However, if there is some

frequency error between the transmitter

and the receiver, the bit decision level

should be adjusted accordingly. In

CC1020

this is done automatically by measuring

the two frequencies and use the average

value as the decision level.

The digital data slicer in

CC1020 uses an

average value of the minimum and

maximum frequency deviation detected as

the comparison level. The RXDEV_X[1:0]

and

RXDEV_M[3:0]

the

AFC_CONTROL register are used to set

the expected deviation of the incoming

signal. Once a shift in the received

frequency

larger

than

the

expected

deviation is detected, a bit transition is

recorded and the average value to be

used by the data slicer is calculated.

The minimum number of transitions

required to calculate a slicing level is 3.

That is, a 010 bit pattern (NRZ).

The actual number of bits used for the

averaging can be increased for better data

decision accuracy. This is controlled by

the

SETTLING[1:0]

bits

the

AFC_CONTROL register. If RX data is

present in the channel when the RX chain

is turned on, then the data slicing estimate

will usually give correct results after 3 bit

transitions. The data slicing accuracy will

increase after this, depending on the

SETTLING[1:0] bits. If the start of

transmission occurs after the RX chain

has turned on, the minimum number of bit

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