CC1020-RTR1 datasheet(61/91 Pages) TI

61 / 91 page

CC1020

SWRS046

Page 61 of 92

This function should only be used in

receive mode and is enabled by setting

DCLK_CS = 1 in the INTERFACE register.

The DCLK signal is always logic high

unless carrier sense is indicated. When

carrier sense is indicated the DCLK starts

running. When gating the DCLK signal

with the carrier sense signal at least 2

dummy bits should be added after the data

payload in TX mode. The reason being

that the carrier sense signal is generated

earlier in the receive chain (i.e. before the

demodulator), causing it to be updated 2

bits before the corresponding data is

available on the DIO pin.

In transmit mode DCLK_CS must be set to

0. Refer to

CC1020 Errata Note 002.

22.

PA_EN and LNA_EN Digital Output Pins

22.1. Interfacing an External LNA or PA

CC1020 has two digital output pins, PA_EN

and LNA_EN, which can be used to

control an external LNA or PA. The

functionality of these pins are controlled

through the INTERFACE register. The

outputs can also be used as general digital

output control signals.

EXT_PA_POL and EXT_LNA_POL control

the active polarity of the signals.

EXT_PA

and

EXT_LNA

control

the

function of the pins. If EXT_PA = 1, then

the PA_EN pin will be activated when the

internal PA is turned on. Otherwise, the

EXT_PA_POL bit controls the PA_EN pin

directly. If EXT_LNA = 1, then the

LNA_EN pin will be activated when the

internal LNA is turned on. Otherwise, the

EXT_LNA_POL bit controls the LNA_EN

pin directly.

These two pins can therefore also be used

as two general control signals, see section

22.2. In the Chipcon reference design

LNA_EN and PA_EN are used to control

the external T/R switch.

22.2. General Purpose Output Control Pins

The two digital output pins, PA_EN and

LNA_EN, can be used as two general

control signals by setting EXT_PA = 0 and

EXT_LNA = 0. The output value is then

set directly by the value written to

EXT_PA_POL and EXT_LNA_POL.

The LOCK pin can also be used as a

general-purpose output pin. The LOCK pin

is controlled by LOCK_SELECT[3:0] in the

LOCK register. The LOCK pin is low when

LOCK_SELECT[3:0] = 0000, and high

when LOCK_SELECT[3:0] = 0001.

These features can be used to save I/O

pins on the microcontroller when the other

functions associated with these pins are

not used.

22.3. PA_EN and LNA_EN Pin Drive

Figure 35 shows the PA_EN and LNA_EN

pin drive currents. The sink and source

currents have opposite signs but absolute

values are used in Figure 35.

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