CC1020-RTR1 datasheet(73/91 Pages) TI

73 / 91 page

CC1020

SWRS046

Page 73 of 92

AFC_CONTROL Register (0Fh)

NAME

Default

value

Active

Description

AFC_CONTROL[7:6]

SETTLING[1:0]

Controls AFC settling time versus accuracy

0: AFC off; zero average frequency is used in demodulator

1: Fastest settling; frequency averaged over 1 0/1 bit pair

2: Medium settling; frequency averaged over 2 0/1 bit pairs

3: Slowest settling; frequency averaged over 4 0/1 bit pairs

Recommended setting: AFC_CONTROL=3 for higher

accuracy unless it is essential to have the fastest settling

time when transmission starts after RX is activated.

AFC_CONTROL[5:4]

RXDEV_X[1:0]

RX frequency deviation exponent

AFC_CONTROL[3:0]

RXDEV_M[3:0]

RX frequency deviation mantissa

Expected RX deviation should be:

Baud rate · RXDEV_M ·2

(RXDEV_X−3) / 3

To find RXDEV_M given the deviation and RXDEV_X:

RXDEV_M = 3 · deviation ·2

(3−RXDEV_X) / Baud rate

Decrease RXDEV_X and try again if RXDEV_M

<8.

Increase RXDEV_X and try again if RXDEV_M

≥16.

Note: The RX frequency deviation should be close to half the TX frequency deviation for GFSK at 100

kBaud data rate and below. The RX frequency deviation should be close to the TX frequency deviation

for FSK and for GFSK at 100 kBaud data rate and above.

FILTER Register (10h)

NAME

Default

value

Active

Description

FILTER[7]

FILTER_BYPASS

Bypass analog image rejection / anti-alias filter. Set to 1 for

increased dynamic range at high Baud rates.

Recommended setting:

FILTER_BYPASS=0 below 76.8 kBaud,

FILTER_BYPASS=1 for 76.8 kBaud and up.

FILTER[6:5]

DEC_SHIFT[1:0]

Number of extra bits to shift decimator input

(may improve filter accuracy and lower power consumption).

Recommended settings:

DEC_SHIFT=0 when DEC_DIV ≤1 (receiver channel bandwidth

≥ 153.6 kHz),

DEC_SHIFT=1 when optimized sensitivity and 1< DEC_DIV

24 (12.29 kHz < receiver channel bandwidth < 153.6 kHz),

DEC_SHIFT=2 when optimized selectivity and DEC_DIV

≥ 24

(receiver channel bandwidth ≤12.29 kHz)

FILTER[4:0]

DEC_DIV[4:0]

Decimation clock divisor

0: Decimation clock divisor = 1, 307.2 kHz channel filter BW.

1: Decimation clock divisor = 2, 153.6 kHz channel filter BW.

…

30: Decimation clock divisor = 31, 9.91 kHz channel filter BW.

31: Decimation clock divisor = 32, 9.6 kHz channel filter BW.

Channel filter bandwidth is 307.2 kHz divided by the decimation

clock divisor.

CC1020-RTR1 Datenblatt(PDF) 73 Page - Texas Instruments

CC1020-RTR1 Datenblatt(HTML) 73 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Datenblatt Download

Link URL