CC1020-RTR1 datasheet(40/91 Pages) TI

40 / 91 page

CC1020

SWRS046

Page 40 of 92

CS_LEVEL[4:0]

must

changed

accordingly to maintain the same absolute

carrier sense threshold. See Figure 18 for

an explanation of the relationship between

RSSI, AGC and carrier sense settings.

The carrier sense signal can be read as

the CARRIER_SENSE bit in the STATUS

The carrier sense signal can also be made

available at the LOCK pin by setting

LOCK_SELECT[3:0] = 0100 in the LOCK

12.12. Automatic Power-up Sequencing

CC1020 has a built-in automatic power-up

sequencing state machine. By setting the

CC1020 into this mode, the receiver can be

powered-up automatically by a wake-up

signal and will then check for a carrier

signal (carrier sense). If carrier sense is

not detected, it returns to power-down

mode. A flow chart for automatic power-up

sequencing is shown in Figure 19.

The automatic power-up sequencing mode

is selected when PD_MODE[1:0] = 11 in

the MAIN register. When the automatic

power-up sequencing mode is selected,

the functionality of the MAIN register is

changed

and

used

control

the

sequencing.

By setting SEQ_PD = 1 in the MAIN

CC1020 is set in power down

mode.

SEQ_PSEL

the

SEQUENCING register the automatic

power-up sequence is initiated by a

negative transition on the PSEL pin.

If SEQ_PSEL = 0 in the SEQUENCING

sequence is initiated by a negative

transition on the DIO pin (as long as

SEP_DI_DO = 1 in the INTERFACE

Sequence timing is controlled through

RX_WAIT[2:0] and CS_WAIT[3:0] in the

SEQUENCING register.

VCO and PLL calibration can also be done

automatically as a part of the sequence.

This is controlled through SEQ_CAL[1:0]

in the MAIN register. Calibration can be

done every time, every 16

th sequence,

every 256

th sequence, or never. See the

description

for

details.

description of when to do, and how the

VCO and PLL self-calibration is done, is

given in section 15.2 on page 51.

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