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CC1020-RTR1 Datenblatt(PDF) 67 Page - Texas Instruments |
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CC1020-RTR1 Datenblatt(HTML) 67 Page - Texas Instruments |
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67 / 91 page ![]() CC1020 SWRS046 Page 67 of 92 MAIN Register (00h) REGISTER NAME Default value Active Description MAIN[7] RXTX - - RX/TX switch, 0: RX , 1: TX MAIN[6] F_REG - - Selection of Frequency Register, 0: Register A, 1: Register B MAIN[5:4] PD_MODE[1 :0] - - Power down mode 0 (00): Receive Chain in power-down in TX, PA in power-down in RX 1 (01): Receive Chain and PA in power-down in both TX and RX 2 (10): Individual modules can be put in power-down by programming the POWERDOWN register 3 (11): Automatic power-up sequencing is activated (see below) MAIN[3] FS_PD - H Power Down of Frequency Synthesizer MAIN[2] XOSC_PD - H Power Down of Crystal Oscillator Core MAIN[1] BIAS_PD - H Power Down of BIAS (Global Current Generator) and Crystal Oscillator Buffer MAIN[0] RESET_N - L Reset, active low. Writing RESET_N low will write default values to all other registers than MAIN. Bits in MAIN do not have a default value and will be written directly through the configuration interface. Must be set high to complete reset. MAIN Register (00h) when using automatic power-up sequencing (RXTX = 0, PD_MODE[1:0] =11) REGISTER NAME Default value Active Description MAIN[7] RXTX - - Automatic power-up sequencing only works in RX (RXTX=0) MAIN[6] F_REG - - Selection of Frequency Register, 0: Register A, 1: Register B MAIN[5 :4] PD_MODE[1 :0] - H Set PD_MODE[1:0]=3 (11) to enable sequencing MAIN[3:2] SEQ_CAL[1:0] - - Controls PLL calibration before re-entering power-down 0: Never perform PLL calibration as part of sequence 1: Always perform PLL calibration at end of sequence 2: Perform PLL calibration at end of every 16 th sequence 3: Perform PLL calibration at end of every 256 th sequence MAIN[1] SEQ_PD - ↑ ↑1: Put the chip in power down and wait for start of new power-up sequence MAIN[0] RESET_N - L Reset, active low. Writing RESET_N low will write default values to all other registers than MAIN. Bits in MAIN do not have a default value and will be written directly through the configuration interface. Must be set high to complete reset. |
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