CC1020-RTR1 datasheet(22/91 Pages) TI

22 / 91 page

CC1020

SWRS046

Page 22 of 92

Microcontroller Interface

Used in a typical system,

CC1020 will

interface

microcontroller.

This

microcontroller must be able to:

• Program

CC1020 into different modes

via the 4-wire serial configuration

interface (PDI, PDO, PCLK and PSEL)

• Interface

the

bi-directional

synchronous data signal interface (DIO

and DCLK)

• Optionally, the microcontroller can do

data encoding / decoding

• Optionally, the microcontroller can

monitor the LOCK pin for frequency

lock status, carrier sense status or

other status information.

• Optionally, the microcontroller can read

back the digital RSSI value and other

status information via the 4-wire serial

interface

Configuration interface

The microcontroller interface is shown in

Figure 6. The microcontroller uses 3 or 4

I/O pins for the configuration interface

(PDI, PDO, PCLK and PSEL). PDO should

be connected to a microcontroller input.

PDI,

PCLK

and

PSEL

must

microcontroller outputs. One I/O pin can

be saved if PDI and PDO are connected

together and a bi-directional pin is used at

the microcontroller.

The microcontroller pins connected to PDI,

PDO and PCLK can be used for other

purposes when the configuration interface

is not used. PDI, PDO and PCLK are high

impedance inputs as long as PSEL is not

activated (active low).

PSEL has an internal pull-up resistor and

should be left open (tri-stated by the

microcontroller) or set to a high level

during power down mode in order to

prevent a trickle current flowing in the pull-

up.

Signal interface

A bi-directional pin is usually used for data

(DIO) to be transmitted and data received.

DCLK providing the data timing should be

connected to a microcontroller input.

As an option, the data output in receive

mode can be made available on a

separate pin. See section 9.2 on page for

25 further details.

PLL lock signal

Optionally, one microcontroller pin can be

used to monitor the LOCK signal. This

signal is at low logic level when the PLL is

in lock. It can also be used for carrier

sense and to monitor other internal test

signals.

PDI

PCLK

PSEL

DIO

LOCK

Micro-

controller

DCLK

(Optional)

PDO

(Optional)

PDI

PCLK

PSEL

DIO

LOCK

Micro-

controller

DCLK

(Optional)

PDO

(Optional)

Figure 6. Microcontroller interface

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