CC1020-RTR1 datasheet(16/91 Pages) TI

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CC1020

SWRS046

Page 16 of 92

Pin no.

Pin name

Pin type

Description

AGND

Ground (analog)

Exposed die attached pad. Must be soldered to a solid ground plane as

this is the ground connection for all analog modules. See page 64 for

more details.

PCLK

Digital input

Programming clock for SPI configuration interface

PDI

Digital input

Programming data input for SPI configuration interface

PDO

Digital output

Programming data output for SPI configuration interface

DGND

Ground (digital)

Ground connection (0 V) for digital modules and digital I/O

DVDD

Power (digital)

Power supply (3 V typical) for digital modules and digital I/O

DGND

Ground (digital)

Ground connection (0 V) for digital modules (substrate)

DCLK

Digital output

Clock for data in both receive and transmit mode.

Can be used as receive data output in asynchronous mode

DIO

Digital input/output

Data input in transmit mode; data output in receive mode

Can also be used to start power-up sequencing in receive

LOCK

Digital output

PLL Lock indicator, active low. Output is asserted (low) when PLL is in

lock. The pin can also be used as a general digital output, or as receive

data output in synchronous NRZ/Manchester mode

XOSC_Q1

Analog input

Crystal oscillator or external clock input

XOSC_Q2

Analog output

Crystal oscillator

AVDD

Power (analog)

Power supply (3 V typical) for crystal oscillator

AVDD

Power (analog)

Power supply (3 V typical) for the IF VGA

LNA_EN

Digital output

General digital output. Can be used for controlling an external LNA if

higher sensitivity is needed.

PA_EN

Digital output

General digital output. Can be used for controlling an external PA if

higher output power is needed.

AVDD

Power (analog)

Power supply (3 V typical) for global bias generator and IF anti-alias

filter

R_BIAS

Analog output

Connection for external precision bias resistor (82 k

Ω, ± 1%)

AVDD

Power (analog)

Power supply (3 V typical) for LNA input stage

RF_IN

RF Input

RF signal input from antenna (external AC-coupling)

AVDD

Power (analog)

Power supply (3 V typical) for LNA

RF_OUT

RF output

RF signal output to antenna

AVDD

Power (analog)

Power supply (3 V typical) for LO buffers, mixers, prescaler, and first PA

stage

AVDD

Power (analog)

Power supply (3 V typical) for VCO

Analog input

VCO control voltage input from external loop filter

AGND

Ground (analog)

Ground connection (0 V) for analog modules (guard)

AD_REF

Power (analog)

3 V reference input for ADC

AVDD

Power (analog)

Power supply (3 V typical) for charge pump and phase detector

CHP_OUT

Analog output

PLL charge pump output to external loop filter

AVDD

Power (analog)

Power supply (3 V typical) for ADC

DGND

Ground (digital)

Ground connection (0 V) for digital modules (guard)

DVDD

Power (digital)

Power supply connection (3 V typical) for digital modules

PSEL

Digital input

Programming chip select, active low, for configuration interface. Internal

pull-up resistor.

Table 11. Pin assignment overview

Note:

DCLK,

DIO

and

LOCK

are

high-

impedance (3-state) in power down

(BIAS_PD = 1 in the MAIN register).

The exposed die attached pad must be

soldered to a solid ground plane as this is

the main ground connection for the chip.

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