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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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CC1020-RTR1 Datenblatt(PDF) 82 Page - Texas Instruments |
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CC1020-RTR1 Datenblatt(HTML) 82 Page - Texas Instruments |
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82 / 91 page  CC1020 SWRS046 Page 82 of 92 TEST1 Register (21h, for test only) REGISTER NAME Default value Active Description TEST1[7:4] CAL_DAC_OPEN[3:0] 4 - Calibration DAC override value, active when BREAK_LOOP=1 TEST1[3:0] CHP_CO[3:0] 13 - Charge pump current override value TEST2 Register (22h, for test only) REGISTER NAME Default value Active Description TEST2[7] BREAK_LOOP 0 H 0: PLL loop closed 1: PLL loop open TEST2[6] CHP_OVERRIDE 0 H 0: use calibrated value 1: use CHP_CO[3:0] value TEST2[5] VCO_OVERRIDE 0 H 0: use calibrated value 1: use VCO_AO[4:0] value TEST2[4:0] VCO_AO[4:0] 16 - VCO_ARRAY override value TEST3 Register (23h, for test only) REGISTER NAME Default value Active Description TEST3[7] VCO_CAL_MANUAL 0 H Enables “manual” VCO calibration (test only) TEST3[6] VCO_CAL_OVERRIDE 0 H Override VCO current calibration 0: Use calibrated value 1: Use VCO_CO[5:0] value VCO_CAL_OVERRIDE controls VCO_CAL_CLK if VCO_CAL_MANUAL=1. Negative transitions are then used to sample VCO_CAL_COMP. TEST3[5:0] VCO_CO[5:0] 6 - VCO_CAL_CURRENT override value TEST4 Register (24h, for test only) REGISTER NAME Default value Active Description TEST4[7] CHP_DISABLE 0 H Disable normal charge pump operation TEST4[6] CHP_TEST_UP 0 H Force charge pump to output “up” current TEST4[5] CHP_TEST_DN 0 H Force charge pump to output “down” current TEST4[4:3] TM_IQ[1:0] 0 - Value of differential I and Q outputs from mixer when TM_ENABLE=1 0: I output negative, Q output negative 1: I output negative, Q output positive 2: I output positive, Q output negative 3: I output positive, Q output positive TEST4[2] TM_ENABLE 0 H Enable DC control of mixer output (for testing) TEST4[1] TF_ENABLE 0 H Connect analog test module to filter inputs TEST4[0] TA_ENABLE 0 H Connect analog test module to ADC inputs If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test module: INTERFACE[3] = TEST_PD, INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1 and TEST_MODE[2]=1. TEST5 Register (25h, for test only) REGISTER NAME Default value Active Description TEST5[7] F_COMP_ENABLE 0 H Enable frequency comparator output F_COMP from phase detector TEST5[6] SET_DITHER_CLOCK 1 H Enable dithering of delta-sigma clock TEST5[5] ADC_TEST_OUT 0 H Outputs ADC samples on LOCK and DIO, while ADC_CLK is output on DCLK TEST5[4] CHOP_DISABLE 0 H Disable chopping in ADC integrators TEST5[3] SHAPING_DISABLE 0 H Disable ADC feedback mismatch shaping TEST5[2] VCM_ROT_DISABLE 0 H Disable rotation for VCM mismatch shaping TEST5[1:0] ADC_ROTATE[1:0] 0 - Control ADC input rotation 0: Rotate in 00 01 10 11 sequence 1: Rotate in 00 10 11 01 sequence 2: Always use 00 position 3: Rotate in 00 10 00 10 sequence |
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