CC1020-RTR1 datasheet(68/91 Pages) TI

68 / 91 page

CC1020

SWRS046

Page 68 of 92

INTERFACE Register (01h)

NAME

Default

value

Active

Description

INTERFACE[7]

XOSC_BYPASS

Bypass internal crystal oscillator, use external clock

0: Internal crystal oscillator is used, or external sine wave fed

through a coupling capacitor

1: Internal crystal oscillator in power down, external clock

with rail-to-rail swing is used

INTERFACE[6]

SEP_DI_DO

Use separate pin for RX data output

0: DIO is data output in RX and data input in TX. LOCK pin

is available (Normal operation).

1: DIO is always input, and a separate pin is used for RX

data output (synchronous mode: LOCK pin, asynchronous

mode: DCLK pin).

If SEP_DI_DO=1 and SEQ_PSEL=0 in SEQUENCING

power-up sequencing when PD_MODE=3 (power-up

sequencing is enabled).

INTERFACE[5]

DCLK_LOCK

Gate DCLK signal with PLL lock signal in synchronous mode

Only applies when PD_MODE = “01”

0: DCLK is always 1

1: DCLK is always 1 unless PLL is in lock

INTERFACE[4]

DCLK_CS

Gate DCLK signal with carrier sense indicator in

synchronous mode

Use when receive chain is active (in power-up)

Always set to 0 in TX mode.

0: DCLK is independent of carrier sense indicator.

1: DCLK is always 1 unless carrier sense is indicated

INTERFACE[3]

EXT_PA

Use PA_EN pin to control external PA

0: PA_EN pin always equals EXT_PA_POL bit

1: PA_EN pin is asserted when internal PA is turned on

INTERFACE[2]

EXT_LNA

Use LNA_EN pin to control external LNA

0: LNA_EN pin always equals EXT_LNA_POL bit

1: LNA_EN pin is asserted when internal LNA is turned on

INTERFACE[1]

EXT_PA_POL

Polarity of external PA control

0: PA_EN pin is “0” when activating external PA

1: PA_EN pin is “1” when activating external PA

INTERFACE[0]

EXT_LNA_POL

Polarity of external LNA control

0: LNA_EN pin is “0” when activating external LNA

1: LNA_EN pin is “1” when activating external LNA

Note: If TF_ENABLE=1 or TA_ENABLE=1 in TEST4 register, then INTERFACE[3:0] controls analog test

module: INTERFACE[3] = TEST_PD, INTERFACE[2:0] = TEST_MODE[2:0]. Otherwise, TEST_PD=1

and TEST_MODE[2:0]=001.

RESET Register (02h)

NAME

Default

value

Active

Description

RESET[7]

ADC_RESET_N

Reset ADC control logic

RESET[6]

AGC_RESET_N

Reset AGC (VGA control) logic

RESET[5]

GAUSS_RESET_N

Reset Gaussian data filter

RESET[4]

AFC_RESET_N

Reset AFC / FSK decision level logic

RESET[3]

BITSYNC_RESET_N

Reset modulator, bit synchronization logic and PN9

PRBS generator

RESET[2]

SYNTH_RESET_N

Reset digital part of frequency synthesizer

RESET[1]

SEQ_RESET_N

Reset power-up sequencing logic

RESET[0]

CAL_LOCK_RESET_N

Reset calibration logic and lock detector

Note: For reset of CC1020 write RESET_N=0 in the MAIN register. The reset register should not be

used during normal operation.

Bits in the RESET register are self-clearing (will be set to 1 when the reset operation starts). Relevant

digital clocks must be running for the resetting to complete. After writing to the RESET register, the user

should verify that all reset operations have been completed, by reading the RESET_DONE status

CC1020-RTR1 Datenblatt(PDF) 68 Page - Texas Instruments

CC1020-RTR1 Datenblatt(HTML) 68 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Datenblatt Download

Link URL