CC1020-RTR1 datasheet(60/91 Pages) TI

60 / 91 page

CC1020

SWRS046

Page 60 of 92

XOR

Tx out (modulating signal)

Tx data (DIO pin)

XOR

Rx pseudo random sequence

Rx in (Demodulated Rx data)

Rx out (DIO pin)

Tx pseudo random sequence

Figure 34. PN9 pseudo random sequence generator in TX and RX mode

21.

Interrupt on Pin DCLK

21.1. Interrupt upon PLL Lock

In synchronous mode the DCLK pin on

CC1020 can be used to give an interrupt

signal to wake the microcontroller when

the PLL is locked.

PD_MODE[1:0] in the MAIN register

should be set to 01. If DCLK_LOCK in the

INTERFACE register is set to 1 the DCLK

signal is always logic high if the PLL is not

in lock. When the PLL locks to the desired

frequency the DCLK signal changes to

logic 0. When this interrupt has been

detected write PD_MODE[1:0] = 00. This

will enable the DCLK signal.

This function can be used to wait for the

PLL to be locked before the PA is ramped

up in transmit mode. In receive mode, it

can be used to wait until the PLL is locked

before searching for preamble.

21.2. Interrupt upon Received Signal Carrier Sense

In synchronous mode the DCLK pin on

CC1020 can also be used to give an

interrupt signal to the microcontroller when

the RSSI level exceeds a certain threshold

(carrier sense threshold). This function can

be used to wake or interrupt the

microcontroller when a strong signal is

received.

Gating the DCLK signal with the carrier

sense signal makes the interrupt signal.

CC1020-RTR1 Datenblatt(PDF) 60 Page - Texas Instruments

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