CC1020-RTR1 datasheet(29/91 Pages) TI

29 / 91 page

CC1020

SWRS046

Page 29 of 92

REF_DIV (3 bits in the CLOCK_A or

CLOCK_B register), a number between 1

and 7:

DIV

REF

xosc

ref

FSK frequency deviation is programmed in

the DEVIATION register. The deviation

programming is divided into a mantissa

(TXDEV_M[3:0])

and

exponent

(TXDEV_X[2:0]).

Generally REF_DIV should be as low as

possible but the following requirements

must be met

[]

MHz

ref

256

8304

≥

in the frequency band 402 – 470 MHz, and

[]

MHz

ref

512

8304

≥

in the frequency band 804 – 940 MHz.

The PLL output frequency equations

above give the carrier frequency, fc , in

transmit mode (centre frequency). The two

FSK modulation frequencies are given by:

f0 = fc − fdev

f1 = fc + fdev

where fdev is set by the DEVIATION

)

(

−

⋅

TXDEV

ref

dev

TXDEV

in the frequency band 402 – 470 MHz and

)

(

−

⋅

TXDEV

ref

dev

TXDEV

in the frequency band 804 – 940 MHz.

OOK

(On-Off

Keying)

used

TXDEV_M[3:0] = 0000.

The TX_SHAPING bit in the DEVIATION

modulation signal.

In receive mode the frequency must be

programmed to be the LO frequency. Low

side LO injection is used, hence:

fLO = fc − fIF

where fIF is the IF frequency (ideally 307.2

kHz).

11.1. Dithering

Spurious signals will occur at certain

frequencies depending on the division

ratios in the PLL. To reduce the strength of

these spurs, a common technique is to

use a dithering signal in the control of the

frequency dividers. Dithering is activated

by setting the DITHER bit in the FREQ_0

registers. It is recommended to use the

dithering in order to achieve the best

possible performance.

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