CC1020-RTR1 datasheet(64/91 Pages) TI

64 / 91 page

CC1020

SWRS046

Page 64 of 92

TEST1[3:0]: CHP_CO[3:0]

TEST2[4:0]: VCO_AO[4:0]

TEST2[5]: VCO_OVERRIDE

TEST2[6]: CHP_OVERRIDE

TEST3[5:0]: VCO_CO[5:0]

TEST3[6]: VCO_CAL_OVERRIDE

CHP_CO[3:0] is the register setting read

from CHP_CURRENT[3:0], VCO_AO[4:0]

the register setting read from

VCO_ARRAY[4:0] and VCO_CO[5:0] is

the

setting

read

from

VCO_CAL_CURRENT[5:0].

Assume channel 1 defined by register

FREQ_A is currently being used and that

CC1020 should operate on channel 2 next

(to change channel simply write to register

MAIN[6]). The channel 2 frequency can be

set by register FREQ_B which can be

written to while operating on channel 1.

The calibration data must be written to the

TEST1-3 registers after switching to the

next frequency. That is, when hopping to a

new channel write to register MAIN[6] first

and the test registers next. The PA should

be switched off between each hop and the

PLL should be checked for lock before

switching the PA back on after a hop has

been performed.

Note

that

the

override

bits

VCO_OVERRIDE, CHP_OVERRIDE and

VCO_CAL_OVERRIDE must be disabled

when performing a re-calibration.

24.

PCB Layout Recommendations

The top layer should be used for signal

routing, and the open areas should be

filled with metallization connected to

ground using several vias.

The area under the chip is used for

grounding and must be connected to the

bottom ground plane with several vias. In

the Chipcon reference designs we have

placed 9 vias inside the exposed die

attached pad. These vias should be

“tented” (covered with solder mask) on the

component side of the PCB to avoid

migration of solder through the vias during

the solder reflow process.

Each decoupling capacitor should be

placed as close as possible to the supply

pin it is supposed to decouple. Each

decoupling capacitor should be connected

to the power line (or power plane) by

separate vias. The best routing is from the

power line (or power plane) to the

decoupling capacitor and then to the

CC1020 supply pin. Supply power filtering is

very important, especially for pins 23, 22,

20 and 18.

Each decoupling capacitor ground pad

should be connected to the ground plane

using a separate via. Direct connections

between neighboring power pins will

increase noise coupling and should be

avoided unless absolutely necessary.

The external components should ideally

be as small as possible and surface mount

devices are highly recommended.

Precaution should be used when placing

the microcontroller in order to avoid noise

interfering with the RF circuitry.

A CC1020/1070DK Development Kit with

a fully assembled CC1020EMX Evaluation

Module is available. It is strongly advised

that this reference layout is followed very

closely

order

get

the

best

performance. The layout Gerber files are

available from the Chipcon web site.

CC1020-RTR1 Datenblatt(PDF) 64 Page - Texas Instruments

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