CC1020-RTR1 datasheet(37/91 Pages) TI

37 / 91 page

CC1020

SWRS046

Page 37 of 92

-20.0

-10.0

0.0

10.0

20.0

30.0

40.0

50.0

60.0

70.0

80.0

Blocker frequency offset [kHz]

Figure 17. Typical blocker rejection. Carrier frequency set to 868.3072 MHz (25 kHz

channel spacing, 19.2 kHz receiver channel filter bandwidth)

12.8. Linear IF Chain and AGC Settings

CC1020 is based on a linear IF chain

where the signal amplification is done in

an analog VGA (Variable Gain Amplifier).

The gain is controlled by the digital part of

the IF chain after the ADC (Analog to

Digital Converter). The AGC (Automatic

Gain Control) loop ensures that the ADC

operates inside its dynamic range by using

an analog/digital feedback loop.

The maximum VGA gain is programmed

by the VGA_SETTING[4:0] in the VGA3

approximately 3 dB/LSB. The VGA gain

should be set so that the amplified thermal

noise from the front-end balance the

quantization

noise

from

the

ADC.

Therefore the optimum maximum VGA

gain setting will depend on the channel

filter bandwidth.

A digital RSSI is used to measure the

signal strength after the ADC. The

CS_LEVEL[4:0] in the VGA4 register is

used to set the nominal operating point of

the gain control (and also the carrier sense

level). Further explanation can be found in

Figure 18.

The VGA gain will be changed according

to a threshold set by the VGA_DOWN[2:0]

in the VGA3 register and the VGA_UP[2:0]

in the VGA4 register. Together, these two

values specify the signal strength limits

used by the AGC to adjust the VGA gain.

To avoid unnecessary tripping of the VGA,

an extra hysteresis and filtering of the

RSSI samples can be added. The

AGC_HYSTERESIS bit in the VGA2

The time dynamics of the loop can be

altered by the VGA_BLANKING bit in the

ANALOG register, and VGA_FREEZE[1:0]

and VGA_WAIT[2:0] bits in the VGA1

When VGA_BLANKING is activated, the

VGA recovery time from DC offset spikes

after a gain step is reduced.

VGA_FREEZE determines the time to hold

bit synchronization, VGA and RSSI levels

after one of these events occur:

•

RX power-up

•

The PLL has been out of lock

•

Frequency register setting is switched

between A and B

This feature is useful to avoid AGC

operation during start-up transients and to

ensure

minimum

dwell

time

using

CC1020-RTR1 Datenblatt(PDF) 37 Page - Texas Instruments

CC1020-RTR1 Datenblatt(HTML) 37 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91

Datenblatt Download

Link URL