PC87338 datasheet(24/221 Pages) NSC

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CTS1

CTS2

Group 1

UART Clear to Send signals 1 and 2. When low, this signal

indicates that the modem or data transfer device is ready to

exchange data.

The CTS signal is a modem status input signal whose condition can

be tested by reading bit 4 (CTS) of the Modem Status Register

(MSR) for the appropriate serial channel. Bit 4 is the complement of

the CTS signal. Bit 0 (DCTS) of the MSR indicates whether the

CTS input has changed state since the previous reading of the

MSR. CTS has no effect on the transmitter.

If modem status interrupts are enabled, an interrupt is generated

whenever the DCTS bit of the MSR is set.

CTS2 is multiplexed with A13. When CTS2 is not selected, it is

masked to 0.

I/O

Group 6

Data. These signals are bi-directional data lines to the

microprocessor. D0 is the LSB and D7 is the MSB.

DACK0

Group 1

DMA Acknowledge 0. An active low input signal used to

acknowledge DMA request 0 (DRQ0), and to enable the RD and

WR input signals during a DMA transfer. It can be used by either

the FDC, or the SCC2 or the parallel port. If none of them uses this

input signal, it is ignored. If the device which uses this signal is

disabled or configured with no DMA, the signal is also ignored.

Upon reset, it is ignored.

DACK1

Group 1

DMA Acknowledge 1. An active low input signal used to

acknowledge DMA request 1 (DRQ1), and enable the RD and WR

input signals during a DMA transfer. It can be used by one of the

following: FDC, SCC2 or parallel port. If none of them uses this

input signal, it is ignored. If the device which uses this signal is

disabled or configured with no DMA, the signal is also ignored.

Upon reset, it is ignored.

DACK2

Group 1

DMA Acknowledge 2. An active low input signal used to

acknowledge DMA request 2 (DRQ2), and enable the RD and WR

input signals during a DMA transfer. It can be used by one of the

following: FDC, SCC2 or parallel port. If none of them uses this

input signal, it is ignored. If the device which uses this signal is

disabled or configured with no DMA, the signal is also ignored.

Upon reset, it is used by the FDC.

DACK3

Group 1

DMA Acknowledge 3. An active low input signal used to

acknowledge DMA request 3 (DRQ3), and enable the RD and WR

inputs during a DMA transfer. It can be used by one of the following:

FDC, SCC2 or parallel port. If none of them uses this input signal,

it is ignored. If the device which uses this signal is disabled or

configured with no DMA, the signal is also ignored. Upon reset, it is

used by the FDC. DACK3 is multiplexed with DRATE1, MSEN1,

CS0 and SIRQI2.

Symbol

PQFP

TQFP

I/O and

Group #

Function

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