PC87338 datasheet(70/221 Pages) NSC

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3.1.2

System Operation Modes

The FDC operates in PC-AT mode or PS/2 mode. The

active mode is determined by bit 7 of the ASC regis-

ter.

PC-AT Mode

The PC-AT register set is enabled. The DMA enable

bit in the Digital Output Register (DOR) becomes valid

(IRQ6 and DRQ can be put in TRI-STATE). TC and

DENSEL become active high signals (defaults to a

5.25" floppy disk drive).

PS/2 Mode

This mode supports the PS/2 models 50/60/80 config-

uration and register set. The value of the DMA enable

bit in the Digital Output Register (DOR) becomes un-

important (IRQ6 and DRQ signals are always valid).

TC and DENSEL become active low signals (default

to 3.5" floppy drive).

3.2

DATA TRANSFER

3.2.1

Data Rates

The FDC supports the standard PC data rates of 250,

300 and 500 Kbps, as well as1 Mbps and 2 Mbps.

High performance tape and floppy disk drives that are

currently emerging in the PC world, transfer data at

1 Mbps. Very high performance tape drives transfer

data at 2 Mbps. The FDC also supports the perpen-

dicular recording mode, a new format used for some

high capacity disk drives at 1 Mbps.

The internal digital data separator needs no external

components. It improves the window margin perfor-

mance standards of the DP8473, and is compatible

with the strict data separator requirements of floppy

disk drives and tape drives.

The FDC contains write precompensation circuitry

that defaults to 125 nsec for 250, 300, and 500 Kbps

(41.67 nsec at 1 Mbps). These values can be overrid-

den in software to disable write precompensation or to

provide levels of precompensation up to 250 nsec.

The FDC has internal 24 mA data bus buffers which

allow direct connection to the system bus. The inter-

nal 40 mA totem-pole disk interface buffers are com-

patible with both CMOS drive input signals and 150 ¾

resistor terminated disk drive input signals.

3.2.2

The Data Separator

The internal data separator is a fully digital PLL. The

fully digital PLL synchronizes the raw data signal read

from the disk drive. The synchronized signal is used

to separate the encoded clock and data pulses. The

data pulses are broken down into bytes, and then sent

to the microprocessor by the controller.

The FDC supports five data transfer rates: 250, 300,

500 Kbps and 1, 2 Mbps in Modified Frequency Mod-

ulation (MFM) format.

In the PC97338 the FDC sup-

ports also the FM encoded data mode.

The FDC has a dynamic window margin and lock

range performance capable of handling a wide range

of floppy disk drives. In addition, the data separator

operates under a variety of conditions, including high

fluctuations in the motor speed of tape drives that are

compatible with floppy disk drives.

The dynamic window margin is the primary indicator

of the quality and performance level of the data sepa-

rator. It indicates the toleration of the data separator

for Motor Speed Variation (MSV) of the drive spindle

motor and bit jitter (or window margin).

Figure 42 shows the dynamic window margin in the

performance of the FDC at different data rates, gen-

erated using a FlexStar FS-540 floppy disk simulator

and a proprietary dynamic window margin test pro-

gram written by National Semiconductor.

FIGURE 42. PC87338/PC97338 Dynamic

Window Margin Performance

The x axis measures MSV. MSV is translated directly

to the actual rate at which the data separator reads

data from the disk. In other words, a faster than nom-

inal motor results in a higher data rate.

-14 -12 -10 -8 -6 -4 -2 0

2448 10 12 14

Motor Speed Variation (% of Nominal)

250,300, 500 Kbps and 1 Mbps

Typical Performance at 500 Kbps,

VDD = 5.0 V, 25° C

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