PC87338 datasheet(83/221 Pages) NSC

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0 - Normal power.

1 - Trigger power down.

Bit 7 - Software Reset

This bit controls the same kind of software reset of

the FDC as bit 2 of the Digital Output Register

(DOR). The difference is that this bit is automati-

cally cleared to 0 (no reset) 100 nsec after it was

set to 1.

See also “Bit 2 - Reset Controller” on page 78.

0 - No reset. (Default)

1 - Reset.

3.3.8

Data Register (FIFO), Offset 101

The Data Register of the FDC is a read/write register

that is used to transfer all commands, data and status

information between the microprocessor and the

FDC.

During the command phase, the microprocessor

writes command bytes into the Data Register after

polling the RQM (bit 7) and DIO (bit 6) bits in the MSR.

During the result phase, the microprocessor reads re-

sult bytes from the Data Register after polling the

RQM and DIO bits in the MSR.

Use of the FIFO buffer lengthens the interrupt latency

period and, thereby, reduces the chance of a disk

overrun or underrun error occurring. Typically, the

FIFO buffer is used at a 1 Mbps data transfer rate or

with multi-tasking operating systems.

Enabling and Disabling the FIFO Buffer

The 16-byte FIFO buffer can be used for DMA, inter-

rupt, or software polling type transfers during the exe-

cution of a read, write, format or scan command.

The FIFO buffer is enabled and its threshold is set by

the CONFIGURE command.

When the FIFO buffer is enabled, only execution

phase byte transfers use it. If the FIFO buffer is en-

abled, it is not disabled after a software reset if the

LOCK bit is set in the LOCK command.

The FIFO buffer is always disabled during the com-

mand and result phases of a controller operation. A

hardware reset disables the FIFO buffer and sets its

threshold to zero. The MODE command can also dis-

able the FIFO for read or write operations separately.

After a hardware reset, the FIFO buffer is disabled to

maintain compatibility with PC-AT systems.

Burst Mode Enabled and Disabled

The FIFO buffer can be used with burst mode enabled

or disabled by the MODE command.

In burst mode, DRQ or IRQ6 remains active until all of

the bytes have been transferred to or from the FIFO

buffer.

When burst mode is disabled, DRQ or IRQ6 is deac-

tivated for 350 nsec to allow higher priority transfer re-

quests to be processed.

FIFO Buffer Response Time

During the execution phase of a command involving

data transfer to or from the FIFO buffer, the maximum

time the system has to respond to a data transfer ser-

vice request is calculated by the following formula:

Max_Time = (THRESH + 1) x 8 x tDRP – (16 x tICP)

This formula applies for all data transfer rates, wheth-

er the FIFO buffer is enabled or disabled. THRESH is

a 4-bit value programmed by the CONFIGURE com-

mand, which sets the threshold of the FIFO buffer. If

the FIFO buffer is disabled, THRESH is zero in the

above formula. The last term in the formula, (16 x tICP)

is an inherent delay due to the microcode overhead

required by the FDC. This delay is also data rate de-

pendent. Section 8.4.1 on page 203 specifies mini-

mum and maximum values for tDRP and tICP.

The programmable FIFO threshold (THRESH) is use-

ful in adjusting the FDC to the speed of the system. A

slow system with a sluggish DMA transfer capability

requires a high value for THRESH. this gives the sys-

tem more time to respond to a data transfer service

request (DRQ for DMA mode or IRQ6 for interrupt

mode). Conversely, a fast system with quick response

to a data transfer service request can use a low value

for THRESH.

FIGURE 51. FDC Data Register Bitmap

3.3.9

Digital Input Register (DIR),

Offset 111

This read-only diagnostic register is used to detect the

state of the DSKCHG disk interface input signal and

some diagnostic signals. DIR is unaffected by a soft-

ware reset.

The bits of the DIR register function differently de-

pending on whether the FDC is operating in PC-AT

mode or in PS/2 mode.

321

Reset

Required

Data Register

(FIFO)

Offset 101

Data

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