PC87338 datasheet(73/221 Pages) NSC

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3.2.6

FDC Low-Power Mode Logic

The FDC of the Chip supports two low-power modes,

manual and automatic. Other low-power modes (also

referred to as power down) of the Chip are described

in Section 7.1.

In low-power mode, the microcode is driven from the

clock, so it will be disabled while the clock is off. If bit

1 of the Power and Test configuration Register (PTR)

is 1, the FDC clock is disabled upon entering this

mode. Upon entering the power-down state, bit 7, the

RQM (Request For Master) bit, in the Main Status

For details concerning entering and exiting low-power

mode by setting bit 6 of the Data rate Select Register

(DSR) or by executing the LOW PWR option of the

FDC MODE command, see “Recovery from Low-

Power Mode” later in this section, the “Data Rate Se-

lect Register (DSR), Offset 100” on page 82 and Sec-

tion “The MODE Command” on page 101.

The Data rate Select Register (DSR), Digital Output

ter (CCR) are unaffected and remain active in power-

down mode. Therefore, you should make sure that

the motor and drive select signals are turned off.

If the power to an external clock driving the Chip will

be independently removed while the FDC is in power-

down mode, it must not be done until 2 msec after the

LOW PWR option of the FDC MODE command is is-

sued.

Manual Low-Power Mode

Manual low power is enabled by writing a 1 to bit 6 of

the DSR. The chip will power down immediately. This

bit will be cleared to 0 after power up.

Manual low power can also be triggered by the MODE

command. Manual low power mode functions as a

logical OR function between the DSR low power bit

and the LOW PWR option of the MODE command.

Automatic Low-Power Mode

Automatic low power mode switches the controller

into low power 500 msec (at the 500 Kbps MFM data

rate) after it has entered the Idle state. Once automat-

ic low-power mode is set, it does not have to be set

again, and the controller automatically goes into low

power mode after entering the Idle state.

Automatic low-power mode can only be set with the

LOW PWR option of the MODE command.

Recovery from Low-Power Mode

There are two ways the FDC section can recover from

the power-down state.

Power up is triggered by a software reset via the DOR

or DSR. Since a software reset requires initialization

of the controller, this method might be undesirable.

Power up is also triggered by a read or write to either

the Data Register (FIFO) or Main Status Register

(MSR). This is the preferred way to power up since all

internal register values are retained. It may take a few

milliseconds for the clock to stabilize, and the micro-

processor will be prevented from issuing commands

during this time through the normal MSR protocol.

That means that bit 7, the Request for Master (RQM)

bit, in the MSR will be a 0 until the clock has stabilized.

When the controller has completely stabilized after

power up, the RQM bit in the MSR is set to 1 and the

controller can continue where it left off.

3.2.7

Reset

The FDC can be reset by hardware or software. A

hardware reset consists of pulsing the Master Reset

(MR) input signal. A hardware reset sets all of the

user addressable registers and internal registers to

their default values. The SPECIFY command values

are unaffected by reset, so they must be initialized

again.

The major default conditions affected by reset are:

• FIFO disabled

• DMA disabled

• Implied seeks disabled

• Drive polling enabled

A software reset can be triggered by bit 2 of the Digital

Output Register (DOR) or bit 7 of the Data rate Select

of DOR does not clear itself.

If the LOCK bit in the LOCK command was set to 1

before the software reset, the FIFO, THRESH, and

PRETRK parameters in the CONFIGURE command

will be retained. In addition, the FWR, FRD, and BST

parameters in the MODE command will be retained if

LOCK is set to 1. This function eliminates the need for

total initialization of the controller after a software re-

set.

After a hardware (assuming the FDC is enabled in the

FER) or software reset, the Main Status Register

(MSR) is immediately available for read access by the

microprocessor. It will return a 00h value until all the

internal registers have been updated and the data

separator is stabilized.

When the controller is ready to receive a command

byte, the MSR returns a value of 80h (Request for

Master (RQM, bit 7) bit is set). The MSR is guaran-

teed to return the 80h value within 2.5

µsec after a

hardware or software reset. All other user address-

able registers other than the Main Status Register

(MSR) and Data Register (FIFO) can be accessed at

any time, even during software reset.

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