PC87338 datasheet(87/221 Pages) NSC

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During a write operation, an underrun error terminates

the execution phase after the controller has written

the remaining bytes of the sector with the last correct-

ly written byte to the FIFO. Whether there is an error

or not, an interrupt is generated at the end of the exe-

cution phase, and is cleared by reading the first result

phase byte.

DACK asserted alone, without a RD or WR pulse, is

also counted as a transfer. If pulses of RD or WR are

not being issued for each byte, a DACK pulse must be

issued for each byte so that the Floppy Disk Control-

ler(FDC) can count the number of bytes correctly.

The VERIFY command, allows easy verification of

data written to the disk without actually transferring

the data on the data bus.

Interrupt Transfer Mode - FIFO Disabled

If interrupt transfer (non-DMA) mode is selected,

IRQ6 is asserted instead of DRQ, when each byte is

ready to be transferred.

The Main Status Register (MSR) should be read to

verify that the interrupt is for a data transfer. The RQM

and NON DMA bits (bits 7 and 5, respectively) in the

MSR are set to 1. The interrupt is cleared when the

byte is transferred to or from the Data Register

(FIFO). To transfer the data in or out of the Data reg-

ister, you must use the address bits of the FDC to-

gether and RD or WR must be active, i.e., A2-0 must

be valid. It is not enough to just assert the address bits

of the FDC. RD or WR must also be active for a read

or write transfer to be recognized.

The microprocessor should transfer the byte within

the data transfer service time (see Section 3.3.8 on

page 83). If the byte is not transferred within the time

allotted, an overrun error is indicated in the result

phase when the command terminates at the end of

the current sector.

An interrupt is also generated after the last byte is

transferred. This indicates the beginning of the result

phase. The RQM and DIO bits (bits 7 and 6, respec-

tively) in the MSR are set to 1, and the NON DMA bit

(bit 5) is cleared to 0. This interrupt is cleared by read-

ing the first result byte.

Interrupt Transfer Mode - FIFO Enabled

Interrupt transfer (non-DMA) mode with the FIFO en-

abled is very similar to interrupt transfer mode with the

FIFO disabled. In this case, IRQ6 is asserted instead

of DRQ, under the same FIFO threshold trigger con-

ditions. The MSR should be read to verify that the in-

terrupt is for a data transfer. The RQM and non-DMA

bits (bits 7 and 5, respectively) in the MSR are set. To

transfer the data in or out of the Data register, you

must use the address bits of the FDC together and

RD or WR must be active, i.e., A2-0 must be valid. It

is not enough to just assert the address bits of the

FDC. RD or WR must also be active for a read or write

transfer to be recognized.

Burst mode may be used to hold the IRQ6 pin active

during a burst, or burst mode may be disabled to tog-

gle the IRQ6 pin for each byte of a burst. The Main

Status Register (MSR) is always valid to the micropro-

cessor. For example, during a read command, after

the last byte of data has been read from the disk and

placed in the FIFO, the MSR still indicates that the ex-

ecution phase is active, and that data needs to be

read from the Data Register (FIFO). Only after the last

byte of data has been read by the microprocessor

from the FIFO does the result phase begin.

The overrun and underrun error procedures for non-

DMA mode are the same as for DMA mode. Also,

whether there is an error or not, an interrupt is gener-

ated at the end of the execution phase, and is cleared

by reading the first result phase byte.

Software Polling

If non-DMA mode is selected and interrupts are not

suitable, the microprocessor can poll the MSR during

the execution phase to determine when a byte is

ready to be transferred. The RQM bit (bit 7) in the

MSR reflects the state of the IRQ6 signal. Otherwise,

the data transfer is similar to the interrupt mode de-

scribed above, whether the FIFO is enabled or dis-

abled.

3.4.3

Result Phase

During the result phase, the microprocessor reads a

series of result bytes from the Data Register (FIFO).

These bytes indicate the status of the command.

They may indicate whether the command executed

properly, or may contain some control information.

See the specific commands in “The FDC Command

Set” on page 91 or “Data Register (FIFO), Offset 101”

on page 83 for details.

These result bytes are read in the order specified for

that particular command. Some commands do not

have a result phase. Also, the number of result bytes

varies with each command. All result bytes must be

read from the Data Register (FIFO) before the next

command can be issued.

As it does for command bytes, the Main Status Reg-

ister (MSR) controls the flow of result bytes, and must

be polled by the software before reading each result

byte from the Data Register (FIFO). The RQM bit (bit

7) and DIO bit (bit 6) of the MSR must both be set be-

fore each result byte can be read.

After the last result byte is read, the Command in

Progress bit (bit 4) of the MSR is cleared, and the con-

troller is ready for the next command.

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