PC87338 datasheet(14/221 Pages) NSC

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FIGURE 88 Extended Control Register 1 ...................................................................................................... 166

FIGURE 88 DMA Control Signals Routing .................................................................................................... 167

FIGURE 88 Extended Control Register 2 ...................................................................................................... 167

FIGURE 88 Transmit FIFO Level ................................................................................................................. 168

FIGURE 88 Receive FIFO Level .................................................................................................................. 168

FIGURE 88 Infrared Control Register 1 ......................................................................................................... 169

FIGURE 88 Pipelined Mode Register ........................................................................................................... 171

FIGURE 88 IInfrared Control Register 2 ........................................................................................................ 171

FIGURE 88 Frame Status Byte Register ....................................................................................................... 172

FIGURE 88 Infrared Control Register 3 ......................................................................................................... 173

FIGURE 88 MIR Pulse Width Register .......................................................................................................... 173

FIGURE 88 SIR Pulse Width Register .......................................................................................................... 174

FIGURE 88 Beginning Flags/Preamble Length Register .............................................................................. 174

FIGURE 88 Intrared Receiver Demodulator Control Register ...................................................................... 175

FIGURE 88 Intrared Transmitter Modulator Control Register ........................................................................ 178

FIGURE 88 CEIR Configuration Register ..................................................................................................... 179

FIGURE 88 Infrared Configuration Register 1 ............................................................................................... 180

FIGURE 88 Infrared Configuration Register 2 ............................................................................................... 180

FIGURE 88 Infrared Configuration Register 3 ............................................................................................... 181

FIGURE 88 Infrared Configuration Register 4 ............................................................................................... 181

FIGURE 89 Load Circuit ................................................................................................................................ 202

FIGURE 90 Testing Specification Standard .................................................................................................. 203

FIGURE 91 Clock Timing .............................................................................................................................. 207

FIGURE 92 CPU Read Timing ...................................................................................................................... 208

FIGURE 93 CPU Write Timing ...................................................................................................................... 208

FIGURE 94 DMA Access Timing ................................................................................................................... 209

FIGURE 95 UART, Sharp-IR and CEIR Timing ............................................................................................ 209

FIGURE 96 SIR, MIR and FIR Timing ........................................................................................................... 210

FIGURE 97 IRSLn Write Timing .................................................................................................................... 210

FIGURE 98 Modem Control Timing ............................................................................................................... 211

FIGURE 99 FDC Write Data Timing .............................................................................................................. 211

FIGURE 100 FDC Read Data Timing ............................................................................................................ 211

FIGURE 101 FDC Control Signals Timing ..................................................................................................... 212

FIGURE 102 Parallel Port Interrupt Timing (Compatible Mode) .................................................................... 212

FIGURE 103 Parallel Port Interrupt Timing (Extended Mode) ....................................................................... 212

FIGURE 104 Parallel Port Data Transfer Timing (Compatible Mode) ........................................................... 213

FIGURE 105 Parallel Port Data Transfer Timing (EPP 1.7 Mode) ............................................................... 213

FIGURE 106 Parallel Port Data Transfer Timing (EPP 1.9 Mode) ............................................................... 214

FIGURE 107 Parallel Port Forward Transfer Timing (ECP Mode) ............................................................... 214

FIGURE 108 Parallel Port Reverse Transfer Timing (ECP Mode) ............................................................... 215

FIGURE 109 System Interrupts Timing ......................................................................................................... 215

FIGURE 110 CS1-0 Signals Timing .............................................................................................................. 215

FIGURE 111 Reset Timing ............................................................................................................................ 215

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