PC87338 datasheet(78/221 Pages) NSC

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The motor enable and drive select signals for drives 2

and 3 are only available when four drives are support-

ed, i.e., when bit 4 of FER is 1, or when drives 2 and

0 are exchanged. These signals require external log-

ic.

FIGURE 47. DOR Register Bitmap

Bits 1,0 - Drive Select

These bits select a drive, so that only one drive se-

lect output signal is active at a time.

See four-drive encoding bit 4 of FER on page 46

and logical drive exchange bits 3,2 of TDR on

page 80 for more information.

00 - Drive 0 is selected. (Default)

01 - Drive 1 is selected.

10 - If four drives are supported, or drives 2 and 0

are exchanged, drive 2 is selected.

11 - If four drives are supported, drive 3 is select-

ed.

Bit 2 - Reset Controller

This bit can cause a software reset. The controller

remains in a reset state until this bit is set to 1.

A software reset affects the CONFIGURE and

MODE commands. See Section 3.6.2 on page 94

and 3.6.7 on page 101, respectively. A software

reset does not affect the Data rate Select Register

(DSR), Configuration Control Register (CCR) and

other bits of this register (DOR).

This bit must be low for at least 100 nsec. There is

enough time during consecutive writes to the DOR

to reset software by toggling this bit.

0 - Reset controller. (Default)

1 - No reset.

Bit 3 - DMA Enable (DMAEN)

In PC-AT mode, this bit enables DMA operations

by controlling the DRQ, DACK, TC and IRQ6 DMA

signals. In PC-AT mode, this bit is set to 0 after re-

set.

In PS/2 mode, this bit is reserved, and DRQ,

DACK, TC and IRQ6 are enabled. During reset,

DRQ, DACK, TC, and IRQ6 remain enabled.

0 - In PC-AT mode, DMA operations are disabled.

DACK and TC are disabled, and DRQ and

IRQ6 are put in TRI-STATE. (Default)

1 - In PC-AT mode, DMA operations are enabled,

i.e., DRQ, DACK, TC and IRQ6 signals are

enabled.

Bit 4- Motor Enable 0

If four drives are supported (bit 4 of the Function

Enable Register (FER) is 1), this bit may control

the motor output signal for drive 0, depending on

the remaining bits of this register. See Table 36.

If two drives are supported (bit 4 of the Function

Enable Register (FER) is 0), this bit controls the

motor output signal for drive 0.

0 - The motor signal for drive 0 is not active.

1 - The motor signal for drive 0 is active.

Bit 5 - Motor Enable 1

If four drives are supported (bit 4 of the Function

Enable Register (FER) is 1), this bit may control

the motor output signal for drive 0, depending on

the remaining bits of this register. See Table 36.

If two drives are supported (bit 4 of the Function

Enable Register (FER) is 0), this bit controls the

motor output signal for drive 1.

0 - The motor signal for drive 1 is not active.

1 - The motor signal for drive 1 is active.

Bit 6 - Motor Enable 2

If drives 2 and 0 are exchanged (see logical drive

exchange bits 3,2 of TDR on page 80), or if four

drives are supported (bit 4 of the Function Enable

put signal for drive 2. See Table 36.

0 - The motor signal for drive 2 is not active.

1 - The motor signal for drive 2 is active.

Bit 7 - Motor Enable 3

If four drives are supported (bit 4 of the Function

Enable Register (FER) is 1), this bit may control

the motor output signal for drive 3, depending on

the remaining bits of this register. See Table 36.

0 - The motor signal for drive 3 is not active.

1 - The motor signal for drive 3 is active.

321

Reset

Required

Digital Output

Offset 010

Reset Controller

Motor Enable 0

Motor Enable 1

Motor Enable 2

Motor Enable 3

Drive Select

DMAEN

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