PC87338 datasheet(86/221 Pages) NSC

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PC-AT Mode

In PC-AT interface mode when the FIFO is disabled,

the controller is in single byte transfer mode. That is,

the system has the time it takes to transfer one byte,

to service a DMA request (DRQ) from the controller.

DRQ is deactivated between bytes.

PS/2 Mode

In PS/2 mode, for DMA transfers with the FIFO dis-

abled, instead of single byte transfer mode, the FIFO

is enabled with THRESH = 0Fh. Thus, DRQ is assert-

ed when one byte enters the FIFO during a read, and

when one byte can be written to the FIFO during a

write. DRQ is deactivated by the leading edge of the

DACK input signal, and is asserted again when DACK

becomes inactive high. This operation is very similar

to burst mode transfer with the FIFO enabled except

that DRQ is deactivated between bytes.

DMA Mode - FIFO Enabled

Read Data Transfers

Whenever the number of bytes in the FIFO is greater

than or equal to (16

− THRESH), a DRQ is generated.

This is the trigger condition for the FIFO read data

transfers from the floppy controller to the micropro-

cessor.

When the last byte in the FIFO has been read, DRQ

becomes inactive. DRQ is asserted again when the

FIFO trigger condition is satisfied. After the last byte

of a sector is read from the disk, DRQ is again gener-

ated even if the FIFO has not yet reached its thresh-

old trigger condition. This guarantees that all current

sector bytes are read from the FIFO before the next

sector byte transfer begins.

Burst Mode Enabled - DRQ remains active until

enough bytes have been read from the controller

to empty the FIFO.

Burst Mode Disabled - DRQ is deactivated after

each read transfer. If the FIFO is not completely

empty, DRQ is asserted again after a 350 nsec de-

lay. This allows other higher priority DMA transfers

to take place between floppy disk transfers.

In addition, this mode allows the controller to work

correctly in systems where the DMA controller is

put into a read verify mode, where only DACK sig-

nals are sent to the FDC, with no RD pulses. This

read verify mode of the DMA controller is used in

some PC software. When burst mode is disabled,

a pulse from the DACK input signal may be issued

by the DMA controller, to correctly clocks data

from the FIFO.

Write Data Transfers

Whenever the number of bytes in the FIFO is less

than or equal to THRESH, a DRQ is generated. This

is the trigger condition for the FIFO write data trans-

fers from the microprocessor to the FDC.

Burst Mode Enabled - DRQ remains active until

enough bytes have been written to the controller to

completely fill the FIFO.

Burst Mode Disabled - DRQ is deactivated after

each write transfer. If the FIFO is not full, DRQ is

asserted again after a 350 nsec delay. Deactiva-

tion of DRQ allows other higher priority DMA trans-

fers to take place between floppy disk transfers.

The FIFO has a byte counter which monitors the num-

ber of bytes being transferred to the FIFO during write

operations whether burst mode is enabled or dis-

abled. When the last byte of a sector is transferred to

the FIFO, DRQ is deactivated even if the FIFO has

not been completely filled. Thus, the FIFO is cleared

after each sector is written. Only after the FDC has

determined that another sector is to be written, is

DRQ asserted again. Also, since DRQ is deactivated

immediately after the last byte of a sector is written to

the FIFO, the system will not be delayed by deactiva-

tion of DRQ and is free to do other operations.

Read and Write Data Transfers

The DACK input signal from the DMA controller may

be held active during an entire burst, or a pulse may

be issued for each byte transferred during a read or

write operation. In burst mode, the FDC deactivates

DRQ as soon as it recognizes that the last byte of a

burst was transferred.

If a DACK pulse is issued for each byte, the leading

edge of this pulse is used to deactivate DRQ. If a

DACK pulse is issued, RD or WR is not required. This

is the case during the read-verify mode of the DMA

controller.

If DACK is held active during the entire burst, the trail-

ing edge of the RD or WR pulse is used to deactivate

DRQ. DRQ is deactivated within 50 nsec of the lead-

ing edge of DACK, RD, or WR. This quick response

should prevent the DMA controller from transferring

extra bytes in most applications.

Overrun Errors

An overrun or underrun error terminates the execution

of a command, if the system does not transfer data

within the allotted data transfer time. (See Section

3.3.8 on page 83

), This puts the controller in the result

phase.

During a read overrun, the microprocessor is required

to read the remaining bytes of the sector before the

controller asserts IRQ6, signifying the end of execu-

tion.

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