PC87338 datasheet(46/221 Pages) NSC

46 / 221 page

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1 - In Legacy mode, SCC1 can be accessed at

the address specified by bits 3,2 of the FAR.

In Plug and Play mode, the address is speci-

fied the by S1BAL and S1BAH registers.

Bit 2 - SCC2 Enable

This bit enables SCC2. Any SCC2 interrupt that is

enabled and active or becomes active after SCC2

is disabled asserts the associated IRQ pin when

SCC2 is disabled. If disabling SCC2 via software,

clear ISEN bit (see sec. 5.14.5 on page 159) to 0

before clearing FER bit 2. This is not an issue after

reset because ISEN is 0 until it is written.

0 - Access to SCC2 is blocked and it is in power

down mode. The SCC2 registers retain all

data in power down mode.

1 - In Legacy mode, SCC2 can be accessed at

the address specified by bits 5,4 of the FAR.

In Plug and Play mode, the address is speci-

fied by the S2BAL and S2BAH registers.

Bit 3 - FDC Enable

This bit enables the FDC

0 - Access to the FDC is blocked and it is in pow-

er down mode. The FDC registers retain all

data in power down mode.

1 - FDC can be accessed at the address speci-

fied by bit 5 of FER in Legacy mode, and by

the FBAL and FBAH registers in Plug and

Play mode.

Bit 4 - FDC Four-Drive Encoding

0 - The Chip can control two floppy disk drives di-

rectly without an external decoder.

1 - The two drive select signals and two motor

enable signals from the FDC are encoded so

that four floppy disk drives can be controlled.

See Table 10.

Controlling four FDDs requires an external de-

coder. The pin states shown in Table 10 are a

direct result of the bit patterns shown. All oth-

er bit patterns produce pin states that should

not be decoded to enable any drive or motor.

Bit 5 - Primary or Secondary FDC Address

In Legacy mode, this bit selects the primary or sec-

ondary FDC address. See Table 9.

In Plug and Play mode, this bit is ignored.

TABLE 9. Primary and Secondary Drive Address

Selection

Bits 7,6 - Reserved

These bits are reserved.

Bit 5 of FER

PC-AT Mode

Primary: 3F0-7h

Secondary: 370-7h

TABLE 10. Encoded Drive and Motor Pin Information (Bit 4 of FER = 1)

Note:

When bit 4 of the FER register = 1, MTR1 presents a pulse that is the inverted image of the IOW strobe. This

inverted pulse is active whenever an I/O write to address 3F2h or 372h takes place. This pulse is delayed by

25 - 80 nsec after the leading edge of IOW and its leading edge can be used to clock data into an external

Digital Output Register

Drive Control Pins

Decoded Functions

76543210

MTR1 MTR0

DR1

DR0

Note

Activate drive 0 and motor 0

Note

Activate drive 1 and motor 1

xxxx

Note

Activate drive 2 and motor 2

xxxxx

Note

Activate drive 3 and motor 3

Note

Activate drive 0 and deactivate motor 0

Note

Activate drive 1 and deactivate motor 1

xxxx

Note

Activate drive 2 and deactivate motor 2

xxxxx

Note

Activate drive 3 and deactivate motor 3

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