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PC87338 Datenblatt(PDF) 71 Page - National Semiconductor (TI)

[Old version datasheet] Texas Instruments acquired National semiconductor.
Teilenummer PC87338
Bauteilbeschribung  ACPI 1.0 and PC98/99 Compliant SuperI/O
PDF  221 Pages
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Hersteller  NSC [National Semiconductor (TI)]
Direct Link  http://www.national.com
Logo NSC - National Semiconductor (TI)

PC87338 Datenblatt(HTML) 71 Page - National Semiconductor (TI)

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The dynamic window margin performance curve also
indicates how much bit jitter (or window margin) can
be tolerated by the data separator. This parameter is
shown on the y-axis of the graph. Bit jitter is caused
by the magnetic interaction of adjacent data pulses on
the disk, which effectively shifts the bits away from
their nominal positions in the middle of the bit window.
Window margin is commonly measured as a percent-
age. This percentage indicates how far a data bit can
be shifted early or late with respect to its nominal bit
position, and still be read correctly by the data sepa-
rator. If the data separator cannot correctly decode a
shifted bit, then the data is misread and a CRC error
results.
The dynamic window margin performance curve sup-
plies two pieces of information:
The maximum range of MSV (also called “lock
range”) that the data separator can handle with no
read errors.
The maximum percentage of window margin (or
bit jitter) that the data separator can handle with no
read errors.
Thus, the area under the dynamic window margin
curves in Figure 42 is the range of MSV and bit jitter
that the FDC can handle with no read errors. The in-
ternal digital data separator of the FDC performs
much better than comparable digital data separator
designs, and does not require any external compo-
nents.
The controller maximizes the internal digital data sep-
arator by implementing a read algorithm that enhanc-
es the lock characteristics of the fully digital Phase-
Locked Loop (PLL). The algorithm minimizes the ef-
fect of bad data on the synchronization between the
PLL and the data.
It does this by forcing the fully digital PLL to re-lock to
the clock reference frequency any time the data sep-
arator attempts to lock to a non-preamble pattern.
See the state diagram of this read algorithm in Figure
43.
FIGURE 43. Read Algorithm State Diagram
3.2.3
Perpendicular Recording Mode
Support
The FDC is fully compatible with perpendicular re-
cording mode disk drives at all data transfer rates.
These perpendicular drives are also called 4 Mbyte
(unformatted) or 2.88 Mbyte (formatted) drives. This
refers to their maximum storage capacity.
Perpendicular recording orients the magnetic flux
changes (which represent bits) vertically on the disk
surface, allowing for a higher recording density than
conventional longitudinal recording methods. This in-
creased recording density increases data rate by up
to 1 Mbps, thereby doubling the storage capacity. In
addition, the perpendicular 2.88 MB drive is read/write
compatible with 1.44 MB and 720 KB diskettes (500
Kbps and 250 Kbps respectively).
The 2.88 MB drive has unique format and write data
timing requirements due to its read/write head and
pre-erase head design. This is illustrated in Figure 44.
Not
6th Bit
Read Gate = 1
Read Gate = 0
PLL
to data,
wait 6 bits.
3 Address
Not Found
Wait for
that is not a
bit.
Bit is
Preamble
Bit is Not
Preamble
3 Address
Marks
Check for
3 address
mark bytes.
Not 3rd
Address Mark
PLL idle
locked
to clock.
Operation
Completed
Read ID
field or
data field.
Found
locking
1st bit
preamble
Marks



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