| Datenblatt-Suchmaschine für elektronische Bauteile |
|
PC87338 Datenblatt(PDF) 56 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
PC87338 Datenblatt(HTML) 56 Page - National Semiconductor (TI) |
|
56 / 221 page ![]() 56 www.national.com 2.3.18 SuperI/O Chip Configuration Register 1 (SCF1), Index 18h Upon reset, SCF1 is initialized to xx00000x. FIGURE 19. SCF1 Register Bitmap Bit 0 - Reserved This bit is reserved. Bits 2,1 - ECP DMA Number Reported ECP DMA number, as reflected on bits 1,0 of the CNFGB ECP register. Bit 2 of SCF1 is reflected on bit 1 of CNFGB and bit 1 of SCF1 on bit 0 of CNFGB. Microsoft’s ECP Protocol and ISA Interface Stan- dard defines these bits as shown in Table 18. TABLE 18. ECP DMA Option Selection Bits 5-3 - Parallel Port DMA Plug and Play Support Upon reset these bits are initialized to 000. When a DMA request signal, i.e., DRQ0, DRQ1, DRQ2 or DRQ3, is not configured as an FDC DMA request signal, a parallel port DMA request signal or a SCC2 DMA request signal, it is in TRI-STATE. When a DMA acknowledge signal, i.e., DACK0, DACK1, DACK2 or DACK3, is not configured as an FDC DMA acknowledge signal, a parallel port DMA acknowledge signal or a SCC2 DMA ac- knowledge signal, it is ignored. TABLE 19. Parallel Port Plug and Play DMA Set- tings Bits 7-6 - Reserved These bits are reserved. Bit 2 Bit 1 Selected DMA Option 0 0 Jumpered 8-bit DMA (Default) 0 1 DMA Channel 1 selected 1 0 DMA Channel 2 selected 1 1 DMA Channel 3 selected Reserved Reserved Reserved ECP DMA Number Parallel Port DMA Plug and Play Support 76 543 21 0 Register 1 (SCF1) Reset Required Index 18h x 0 0 0 0 0 x x SuperI/O Chip Configuration Bit 5 Bit 4 Bit 3 Parallel Port DMA Plug and Play Setting 0 0 0 Disabled. Parallel port’s DMA is not connected to any ISA DMA channel, i.e., it is not connected to any of the chip’s DMA pins. It is the software’s responsibility to route all DMA sources onto the ISA DMA channels correctly. 0 0 1 Parallel port‘s DMA request and acknowledge signals are connected to DRQ0 and DACK0 pins. 0 1 0 Parallel port‘s DMA request and acknowledge signals are connected to DRQ1 and DACK1 pins. 0 1 1 Parallel port‘s DMA request and acknowledge signals are connected to DRQ2 and DACK2 pins. 1 0 0 Parallel port‘s DMA request and acknowledge signals are connected to DRQ3 and DACK3 pins. 101 Reserved 110 Reserved 111 Reserved |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |