PC87338 datasheet(22/221 Pages) NSC

22 / 221 page

www.national.com

1.2

SIGNAL/PIN DESCRIPTIONS

Table 1 lists the signals of the Chip in alphabetical order. It also shows the pin associated with each signal for

the Plastic Quad Flatpack, (PQFP) and Thin Quad Flatpack (TQFP) options. The I/O column describes whether

the pin is an input, output, or bidirectional pin (marked as I, O or I/O, respectively). This column also specifies

which group in Section 8.2 describes the pin’s DC characteristics.

Refer to the glossary for an explanation of abbreviations and terms used in this table and throughout this docu-

ment. Use the Table of Contents to find more information about each register.

TABLE 1. Signal/Pin Description Table

Symbol

PQFP

TQFP

I/O and

Group #

Function

A10

A11

A12

A13

A14

A15

Group 1

Address. These address lines from the microprocessor determine

which internal register is accessed. The values of A15-0 have no

effect during DMA transfers.

If CFG0 = 0 during reset, A15-0 are used for address decoding.

If CFG0 = 1 during reset, only A10-0 are used for address

decoding, and A15-11 are ignored (masked to 0).

In Legacy mode, A10 is used only for ECP decoding.

A15-11 are multiplexed with SCC2’s signals.

ACK

Group 3

Acknowledge. This parallel port input signal is pulsed low by an

external printer to indicate it received data from the parallel port.

This pin is internally connected to a nominal 25 K

Ω pull-up resistor.

ACK is multiplexed with DR1. (See Table 72 for more information).

ADRATE0

ADRATE1

Group 10

Additional Data Rate signals 0 and 1. These FDC output signals

are provided in addition to DRATE1,0 and have a similar function.

They reflect the currently selected FDC data rate, (bits 0 and 1 in

the Configuration Control Register (CCR) or the Data Rate Select

ADRATE0 is configured when bit 0 of ASC is 1. ADRATE1 is

configured when bit 4 of ASC is 1.

ADRATE0 is multiplexed with IRQ5 and ADRATE1 is multiplexed

with DENSEL.

AEN

Group 1

Address Enable. When set to 1, this pin enables DMA addressing

and disables the microprocessor Address. The address lines

disabled will be A15-0 or A10-0, depending on whether CFG0 was

set to 0 or 1 during reset (respectively).

Access during DMA transfer is NOT affected by this pin.

AFD

Group 11

Automatic Feed XT. When low this parallel port signal indicates to

the external printer that it should automatically line feed after each

Carriage Return byte. This signal enters a TRI-STATE® condition

within 10 nsec after a 0 is loaded into the Control Register bit.

An external 4.7 K

Ω pull-up resistor should be attached to this pin.

AFD is multiplexed with DSTRB and DENSEL. See Table 72 for

more information.

PC87338 Datenblatt(PDF) 22 Page - National Semiconductor (TI)

PC87338 Datenblatt(HTML) 22 Page - National Semiconductor (TI)

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datenblatt Download

Link URL