PC87338 datasheet(81/221 Pages) NSC

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FIGURE 49. MSR Register Bitmap

Bit 0 - Drive 0 Busy

This bit indicates whether or not drive 0 is busy.

It is set to 1 after the last byte of the command

phase of a SEEK or RECALIBRATE command is

issued for drive 0.

This bit is cleared to 0 after the first byte in the re-

sult phase of the SENSE INTERRUPT command

is read for drive 0.

0 - Not busy.

1 - Busy.

Bit 1 - Drive 1 Busy

This bit indicates whether or not drive 1 is busy.

It is set to 1 after the last byte of the command

phase of a SEEK or RECALIBRATE command is

issued for drive 1.

This bit is cleared to 0 after the first byte in the re-

sult phase of the SENSE INTERRUPT command

is read for drive 1.

0 - Not busy.

1 - Busy.

Bit 2 - Drive 2 Busy

This bit indicates whether or not drive 2 is busy.

It is set to 1 after the last byte of the command

phase of a SEEK or RECALIBRATE command is

issued for drive 2.

This bit is cleared to 0 after the first byte in the re-

sult phase of the SENSE INTERRUPT command

is read for drive 2.

0 - Not busy.

1 - Busy.

Bit 3 - Drive 3 Busy

This bit indicates whether or not drive 3 is busy.

It is set to 1 after the last byte of the command

phase of a SEEK or RECALIBRATE command is

issued for drive 3.

This bit is cleared to 0 after the first byte in the re-

sult phase of the SENSE INTERRUPT command

is read for drive 3.

0 - Not busy.

1 - Busy.

Bit 4 - Command in Progress

This bit indicates whether or not a command is in

progress. It is set after the first byte of the com-

mand phase is written. This bit is cleared after the

last byte of the result phase is read.

If there is no result phase in a command, the bit is

cleared after the last byte of the command phase

is written.

0 - No command is in progress.

1 - A command is in progress.

Bit 5 - Non-DMA Execution

This bit indicates whether or not the controller is in

the execution phase of a byte transfer operation in

non-DMA mode.

This bit is used for multiple byte transfers by the

microprocessor in the execution phase through in-

terrupts or software polling.

0 - The FDC is not in the execution phase.

1 - The FDC is in the execution phase.

Bit 6 - Data I/O (Direction)

Indicates whether the controller is expecting a byte

to be written or read, to or from the Data Register

(FIFO).

0 - Data will be written to the FIFO.

1 - Data will be read from the FIFO.

Bit 7 - Request for Master (RQM)

This bit indicates whether or not the controller is

ready to send or receive data from the micropro-

cessor through the Data Register (FIFO). It is

cleared to 0 immediately after a byte transfer and

is set to 1 again as soon as the disk controller is

ready for the next byte.

During a Non-DMA execution phase, this bit indi-

cates the status of the interrupt.

0 - Not ready. (Default)

1 - Ready to transfer data.

321

Reset

Required

Main Status

Offset 100

Drive 2 Busy

Non-DMA Execution

Data I/O Direction

RQM

Drive 1 Busy

Drive 3 Busy

Command in Progress

Drive 0 Busy

PC87338 Datenblatt(PDF) 81 Page - National Semiconductor (TI)

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