PC87338 datasheet(94/221 Pages) NSC

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3.6.2

The CONFIGURE Command

The CONFIGURE command controls some operation

modes of the controller. It should be issued during the

initialization of the FDC after power up.

The bits in the CONFIGURE registers are set to their

default values after a hardware reset.

Command Phase

Third Command Phase Byte

Bits 3-0 - The FIFO Threshold (THRESH)

These bits specify the threshold of the FIFO during

the execution phase of read and write data trans-

fers.

This value is programmable from 00 to 0F hex. A

software reset sets this value to 00 if the LOCK bit

(bit 7 of the opcode of the LOCK command) is 0. If

the LOCK bit is 1, THRESH retains its value.

Use a high value of THRESH for systems that re-

spond slowly and a low value for fast systems.

Bit 4 - Disable Drive Polling (POLL)

This bit enables and disabled drive polling. A soft-

ware reset clears this bit to 0.

When drive polling is enabled, an interrupt is gen-

erated after a reset.

When drive polling is disabled, if the CONFIGURE

command is issued within 500 msec of a hardware

or software reset, then an interrupt is not generat-

ed. In addition, the four SENSE INTERRUPT com-

mands to clear the Ready Changed State of the

four logical drives is not required.

0 - Enable drive polling. (Default)

1 - Disable drive polling.

Bit 5 - Enable FIFO (FIFO)

This bit enables and disables the FIFO for execu-

tion phase data transfers.

If the LOCK bit (bit 7 of the opcode of the LOCK

command) is 0, a software reset disables the

FIFO, i.e., sets this bit to 1.

If the LOCK bit is 1, this bit retains its previous val-

ue after a software reset.

0 - FIFO enabled for read and write operations.

1 - FIFO disabled. (Default)

Bit 6 - Enable Implied Seeks (EIS)

This bit enables or disables implied seek opera-

tions. A software reset disables implied seeks, i.e.,

clears this bit to 0.

Bit 5 of the MODE command (Implied Seek (IPS)

can override the setting of this bit and enable im-

plied seeks even if they are disabled by this bit.

When implied seeks are enabled, a seek or sense

interrupt operation is performed before execution

of the read, write, scan, or verify operation.

0 - Implied seeks disabled. The MODE command

can still enable implied seek operations. (De-

fault)

1 - Implied seeks enabled for read, write, scan

and VERIFY operations, regardless of the val-

ue of the IPS bit in the MODE command.

Fourth Command Phase Byte, Bits 7-0,

Precompensation Track Number (PRETRK)

This byte identifies the starting track number for

write precompensation. The value of this byte is

programmable from track 0 (00 hex) to track 255

(FF hex).

If the LOCK bit (bit 7 of the opcode of the LOCK

command) is 0, after a software reset this byte in-

dicates track 0 (00 hex).

If the LOCK bit is 1, PRETRK retains its previous

value after a software reset.

Execution Phase

Internal registers are written.

Result Phase

None.

210

011

000

0 EIS

FIFO

POLL

Threshold (THRESH)

Precompensation Track Number (PRETRK)

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