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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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AD9640/PCB Datenblatt(PDF) 28 Page - Analog Devices |
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AD9640/PCB Datenblatt(HTML) 28 Page - Analog Devices |
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28 / 41 page  AD9640 Preliminary Technical Data Rev. PrD | Page 28 of 41 SPORT serial port. The monitor period timer is reloaded with the value in the SMPR, and the countdown is restarted. Also, the first input sample signal power is updated in the holding register, and the accumulation continues with the subsequent input samples. Figure 24 illustrates the RMS magnitude monitoring logic. For RMS magnitude mode, the value in the PMV is a 20 bit fixed point number. The equation shown below can be used to determine the RMS magnitude in dBFS from the MAG value in the register. Note that if the signal monitor period (SMP) is a power of 2, the 2nd term in the equation goes to zero. RMS_Magnitude 20 log MAG 2 20 ⎛ ⎜ ⎝ ⎞ ⎟ ⎠ ⋅ 10 log SMP 2 ceil log2 SMP () ⎡⎣ ⎤⎦ ⎡ ⎢ ⎣ ⎤ ⎥ ⎦ ⋅ − := For MS magnitude mode, the value in the PMV is a 20 bit fixed point number. The equation shown below can be used to determine the MS magnitude in dBFS from the MAG value in the register. Note that if the signal monitor period (SMP) is a power of 2, the 2nd term in the equation goes to zero. MS_Magnitude 10 log MAG 2 20 ⎛ ⎜ ⎝ ⎞ ⎟ ⎠ ⋅ 10 log SMP 2 ceil log2 SMP () ⎡⎣ ⎤⎦ ⎡ ⎢ ⎣ ⎤ ⎥ ⎦ ⋅ − := Figure 24. ADC Input RMS Magnitude Monitoring Block Diagram THRESHOLD CROSSING MODE (MODE BITS 1X) In this mode of operation, the magnitude of the input port signal is monitored over a programmable time period (given by SMPR) to count the number of times it crosses a certain programmable threshold value. This mode is set by program- ming Logic 1x (where x is a don’t care bit) in the power-monitor mode bits of the signal monitor control register or by setting the Threshold Crossing Output Enable bit in the Signal monitor SPORT Control Register. Before activating this mode, the user needs to program the 24-bit SMPR and the 13-bit upper threshold register for each individual input port. The same upper threshold register is used for both signal monitoring and gain control (see the ADC Overrange and Gain Control section). After entering this mode, the value in the SMPR is loaded into a monitor period timer, and the countdown is started. The magnitude of the input signal is compared to the upper threshold register (programmed previously) on each input clock cycle. If the input signal has magnitude greater than the upper threshold register, then the internal count register is incremented by 1. The initial value of the internal count register is set to 0. This comparison and increment of the internal count register continues until the monitor period timer reaches a count of 1. When the monitor period timer reaches a count of 1, the value in the internal count register is transferred to the signal monitor holding register, which can be read through the SPI port or output through the SPORT serial port. The monitor period timer is reloaded with the value in the SMPR, and the countdown is started. The internal count register is also cleared to a value of 0. Figure 25 illustrates the threshold crossing logic. The value in the PMV is the number of samples that have a magnitude greater than the threshold register. POWER MONITOR HOLDING REGISTER COMPARE A > B UPPER THRESHOLD REGISTER COMPARE A > B TO MEMORY MAP FROM MEMORY MAP FROM MEMORY MAP FROM INPUT PORTS LOAD CLEAR LOAD IS COUNT = 1? DOWN COUNTER TO INTERRUPT CONTROLLER POWER MONITOR PERIOD REGISTER B A Figure 25. ADC Input Threshold Crossing Block Diagram ADDITIONAL CONTROL BITS For additional flexibility in the signal monitoring process, two control bits are provided in the power-monitor control register. They are the signal monitor enable bit and the complex power bit. Signal monitor Enable Bit The signal monitor enable bit located in bit 0 or register 0x112 enables operation of the signal monitor block. If the signal monitor function is not needed in a particular application then this bit should be cleared to conserver power. Measure Complex Power Bit When this bit is set the part assumes that Channel A is digitizing the I data and Channel B is digitizing the Q data for a complex input signal (or vice versa). In this mode the power reported is the sqrt(I^2 + Q^2). This complex power measurement result is presented in the Channel A signal monitor value register if the signal monitor mode bits are set to 00. The channel B signal monitor will continue to compute the channel B value. |
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