AD9640SLASHPCB datasheet(35/41 Pages) AD

35 / 41 page

Preliminary Technical Data

AD9640

Rev. PrD | Page 35 of 41

EXTERNAL MEMORY MAP

Table 6. Memory Map Register

Addr.

(Hex)

Parameter

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default

Notes/

Comments

Chip Configuration Registers

SPI Port

Configuration

(global)

LSB first

Soft reset

LSB first

0x18

The nibbles

should be

mirrored so

that LSB- or

MSB-first

mode register

correctly

regardless of

shift mode.

Chip ID

(global)

8-bit Chip ID Bits 7:0

(AD9640 = 0x11), (default)

0x0F

Read

Only

Default is

unique chip

ID, different

for each

device. This is

a read-only

Chip Grade

(global)

Speed Grade ID 4:3

00 = 80 MSPS

01 = 105 MSPS

10 = 125 MSPS

11 = 150 MSPS

Read

only

Speed Grade

ID used to

differentiate

devices.

Channel Index and Transfer Registers

Channel Index

Data

Channel B

(default)

Data

Channel A

(default)

0x03

Bits are set to

determine

which device

on chip

receives the

next write

command.

Applies to

local registers

Device Update

Transfer

0x00

Synchronousl

transfers data

from the

master shift

slave.

ADC Functions

Power modes

External

Power

Down Pin

Function

(global)

0 = pdwn

1 = stndby

Internal power-down

mode

(local)

00—normal operation

01—full power-down

10—standby

11—normal operation

0x00

Determines

various

generic

modes of chip

operation.

Global clock

(global)

Duty cycle

stabilize

(default)

0x01

Clock divide

(global)

Clock Divide Ratio

000 = divide by 1

001 = divide by 2

010 = divide by 3

011 = divide by 4

100 = divide by 5

101 = divide by 6

110 = divide by 7

111 = divide by 8

0x00

Clock divide

values other

than 000

automatically

causes the

Duty Cycle

Stabilization

to become

active

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