AD9640SLASHPCB datasheet(36/41 Pages) AD

36 / 41 page

AD9640

Preliminary Technical Data

Rev. PrD | Page 36 of 41

Addr.

(Hex)

Parameter

Name

Bit 7

(MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Default

Value

(Hex)

Default

Notes/

Comments

Test Mode

(local)

Reset PN23

gen

Reset

PN9 gen

Output test mode

000—off (default)

001—midscale short

010—+positive FS

011—−negative FS

100—alternating checker board

101—PN 23 sequence

110—PN 9 sequence

111—one/zero word toggle

0x00

When set, the

test data is

placed on the

output pins in

place of

normal data.

Bist enable

(local)

Reset

BIST

Sequence

BIST

Enable

0x00

Offset adjust

(local)

Offset Adjust in LSBs from +31 to -32 (twos compliment format)

0x00

Output Mode

Drive

Strength

0—3.3V

CMOS or

ANSI LVDS

1—1.8V

CMOS or

Reduced

LVDS

(global)

Output

Type

0 = CMOS

1 = LVDS

(global)

Interleaved

CMOS

(global)

Output

Enable

Bar

(local)

Output

invert

(local)

00—offset binary 01—

twos complement

01—greycode 11—

offset binary (local)

0x00

Configures the

outputs and

the format of

the data.

Output Adjust

(global)

CMOS 3.3V Drive

Strength (00 is lowest

drive and 11 is highest

drive)

CMOS 1.8 V Drive

Strength (00 is lowest

drive and 11 is highest

drive)

0x02

Determines

CMOS output

drive strength

– Selecting

higher drive

strengths can

affect

converter

performance

Clock Phase

Control

(global)

Invert DCO

Clock

Input clock divider phase adjust

000 = no delay

001 = 1 input clock cycle

010 = 2 input clock cycles

011 = 3 input clock cycles

100 = 4 input clock cycles

101 = 5 input clock cycles

110 = 6 input clock cycles

0x00

On devices

that utilize

global clock

divide, allows

selection of

clock delays

into the

dividerb.

Vref Select

(global)

Reference Voltage

Selection

00 = 1.25V pk-pk

01 = 1.5V pk-pk

10 = 1.75V pk-pk

11 = 2.0V pk-pk (default)

0x30

BIST Signature

lsb (local)

BIST Signature [7:0]

0x00

Read Only

BIST Signature

msb (local)

BIST Signature [15:8]

0x00

Read Only

100

Synch_Control

(global)

PM Sync

Enable

Clock

Divider

Sync

Only

Clock

Divider

Sync

Enable

Master

Sync

Enable

0x00

104

Fast Detect

Control (local)

Fast Detect Mode Select [2:0]

Enable

Fast

Detect

0x00

105

Coarse Upper

Threshold (local)

Coarse Upper Threshold [2:0]

0x00

AD9640/PCB Datenblatt(PDF) 36 Page - Analog Devices

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