AD9640SLASHPCB datasheet(24/41 Pages) AD

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AD9640

Preliminary Technical Data

Rev. PrD | Page 24 of 41

ADC OVERRANGE AND GAIN CONTROL

It is desirable to have a mechanism to reliably determine when

the converter is about to be clipped. The standard overflow

indicator provides after the fact information which is of limited

usefulness. Therefore it is useful to have a programmable

threshold below full-scale that would allow time to reduce the

gain before the clip actually occurs. In addition, since input

signals can have significant slew rates, latency of this function is

a big concern. Highly pipelined converters can have significant

latency. A good compromise of this function is to use the

output bits from the first stage of the ADC for this function.

Latency for these output bits is very low, and overall resolution

is not highly significant.

Peak input signals are typically

between full-scale and 6 to 10 dB below full-scale. A 3 or 4 bit

output should give more than adequate range and resolution for

this function.

Via the SPI port, the user can provide a threshold above which a

fast over-range output would be active. As long as the signal is

below that threshold, the output should remain low. This pin

could also be programmed via the SPI port to function as a

traditional over-range pin for customers who currently use this

feature. In this mode, all 14 bits of the converter would be

examined in the traditional manner and the output would be

high for the condition normally defined as overflow. In either

mode, the sign of the data is not considered in the calculation of

the condition. The threshold detection responds identically to

positive and negative signals outside the desired range

(magnitude).

FAST DETECT OVERVIEW

The AD9640 contains circuitry to facilitate fast over-range

detection allowing very flexible external gain control

implementations. Each ADC has four Fast Detect (FD) bits that

are utilized to output information about the current state of the

ADC input level. The FD bit function is programmable

allowing range information to be output from several points in

the internal data path. These bits can also be set up to indicate

the presence of overrange or underrange conditions according

to programmable threshold levels. Table X.x below shows the 6

configurations available for the Fast Detect bits. These

configurations are selecting by setting bits 3:1 in the register at

SPI address 0x104.

Table xx. Fast Detect Bit Configuration Settings

Fast Detect Mode

Select - Register

104h<3:1>

Information Presented on

FD Bits[3:0]

000

ADC Fast Magnitude[3:0]

001

ADC Fast Magnitude[2:0], OVR

010

ADC Fast Magnitude[2:1], OVR, F_LT

011

ADC Fast Magnitude[2:1], C_UT, F_LT

100

OVR, C_UT, F_UT, F_LT

101

OVR, F_UT, IG, DG

ADC FAST MAGNITUDE

When the FD bits are configured to output the ADC fast

magnitude the information presented is the ADC level with

only a 1 clock cycle latency. Using the FD bits in this

configuration provides the earliest possible level indication

information. Since this information is provided from early in

the data path there is a significant uncertainty in the level

indicated. The nominal levels along with the uncertainty

indicated by the ADC fast magnitude are shown in table x.x.

Table xx. ADC Fast Magnitude Bits Nomimal Levels (Using

Mag[3:0])

ADC_Fast_Mag[3:0]

Nominal Input

magnitude in

dB below FS

Nominal Input

magnitude

Uncertainty in dB

0000

-30.14

+12.07 to Min

0001

-18.07

+6.03/-12.07

0010

-12.04

+3.52/-6.03

0011

-8.52

+2.5/-3.52

0100

-6.02

+1.94/-2.5

0101

-4.08

+1.58/-1.94

0110

-2.5

+1.34/-1.58

0111

-1.16

+1.16/-1.34

1000

-0.28

+0.28/-0.88

When fast detect modes 001, 010, or 011 are selected a subset of

the FD bits are available. Table xx shows the corresponding

ADC input levels when Fast Magnitude[2:0] is selected using

001.

Table xx. ADC Fast Magnitude Bits Nomimal Levels (Using

Mag[2:0])

ADC_Fast_Mag[2:0]

Nominal Input

magnitude in

dB below FS

Nominal Input

magnitude

Uncertainty in dB

000

-30.14

+12.07 to Min

001

-18.07

+6.03/-12.07

010

-12.04

+3.52/-6.03

011

-8.52

+2.5/-3.52

100

-6.02

+1.94/-2.5

101

-4.08

+1.58/-1.94

110

-2.5

+1.34/-1.58

111

-1.16

+1.16/-1.34

When ADC Fast Magnitude[2:1] is selected the LSB is not

provided. The Input ranges for this mode are shown in Table x.

Table xx. ADC Fast Magnitude Bits Nomimal Levels (Using

Mag[2:1])

ADC_Fast_Mag[2:1]

Nominal Input

magnitude in

dB below FS

Nominal Input

magnitude

Uncertainty in dB

-22.14

+10.1 to Min

-10.10

+4.08/-7.97

-5.00

+2.5/-3.52

-1.48

+1.48/-2.6

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