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AD9640/PCB Datenblatt(PDF) 8 Page - Analog Devices

Teilenummer AD9640/PCB
Bauteilbeschribung  14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
PDF  41 Pages
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9640/PCB Datenblatt(HTML) 8 Page - Analog Devices

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AD9640
Preliminary Technical Data
Rev. PrD | Page 8 of 41
SWITCHING SPECIFICATIONS
Table 4.
AD9640BCPZ-80
AD9640BCPZ-105
AD9640BCPZ-125
AD9640BCPZ-150
Unit
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
CLOCK INPUT PARAMETERS
Maximum Conversion Rate
Full
80
105
125
150
MSPS
Minimum Conversion Rate
Full
10
10
10
10
MSPS
CLK Period(tCLK)
Full
12.5
9.5
8
6.66
ns
CLK Pulse Width High1(tCLKH)
Full
TBD
tCLK/2
TBD
tCLK/2
TBD
tCLK/2
TBD
tCLK/2
ns
CLK Pulse Width Low1 (tCLKL)
Full
TBD
tCLK/2
TBD
tCLK/2
TBD
tCLK/2
TBD
tCLK/2
ns
CLK Pulse Width High2(tCLKH)
Full
TBD
tCLK/2
TBD
tCLK/2
TBD
tCLK/2
TBD
tCLK/2
ns
CLK Pulse Width Low(tCLKL)
Full
TBD
tCLK/2
TBD
tCLK/2
TBD
tCLK/2
TBD
tCLK/2
ns
DATA OUTPUT PARAMETERS
Data Propagation Delay
(tPD)3
Full
TBD
TBD
TBD
TBD
ns
DCO Propagation Delay
(tDCO)
Full
TBD
TBD
TBD
TBD
ns
Setup Time (tS)
Full
8.5
8.5
8.5
8.5
ns
Hold Time (tH)
Full
8.5
8.5
8.5
8.5
ns
Pipeline Delay (Latency)
Full
12
12
12
12
Cycles
Aperture Delay (tA)
Full
TBD
TBD
TBD
TBD
ns
Aperture Uncertainty (Jitter,
tJ)
Full
0.1
0.1
0.1
0.1
ps rms
Wake-Up Time4
Full
TBD
TBD
TBD
TBD
ms
OUT-OF-RANGE RECOVERY
TIME
Full
TBD
TBD
TBD
TBD
Parameter (Conditions)
Min
Typ
Max
Unit
RESET TIMING REQUIREMENTS
tRESL
RESET Width Low
TBD
ns
SYNC TIMING REQUIREMENTS
tSS
SYNC to
↑CLK Setup Time
TBD
ns
tHS
SYNCto
↑CLK Hold Time
TBD
ns
SPI TIMING REQUIREMENTS
tDS
Set-up time between the data and the rising edge of SCLK
5
ns
tDH
Hold time between the data and the rising edge of SCLK
5
ns
tCLK
Period of the SCLK
40
ns
tS
Set-up time between CSB and SCLK
TBD
ns
tH
Hold time between CSB and SCLK
TBD
ns
tHI
Minimum period that SCLK should be in a logic high state
TBD
ns
tLO
Minimum period that SCLK should be in a logic low state
TBD
ns
1 With duty cycle stabilizer (DCS) enabled.
2 With duty cycle stabilizer (DCS) disabled.
3 Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
4 Wake-up time is dependant on the value of the decoupling capacitors.



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