AD9640SLASHPCB datasheet(22/41 Pages) AD

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AD9640

Preliminary Technical Data

Rev. PrD | Page 22 of 41

illustrated in Figure 19.

Figure 19. SNR vs. Input Frequency and Jitter

The clock input should be treated as an analog signal in cases

where aperture jitter may affect the dynamic range of the

AD9640. Power supplies for clock drivers should be separated

from the ADC output driver supplies to avoid modulating the

clock signal with digital noise. Low jitter, crystal-controlled

oscillators make the best clock sources. If the clock is generated

from another type of source (by gating, dividing, or other

methods), it should be retimed by the original clock at the last

step.

Refer to the AN-501 Application Note and the AN-756

Application Note for more in-depth information about jitter

performance as it relates to ADCs. See www.analog.com.

POWER DISSIPATION AND STANDBY MODE

As shown in Figure 20, the power dissipated by the AD9640 is

proportional to its sample rate. In CMOS output mode, the

digital power dissipation is determined primarily by the

strength of the digital drivers and the load on each output bit.

The maximum DRVDD current (IDRVDD) can be calculated as:

CLK

LOAD

DRVDD

where N is the number of output bits, 14 in the case of the

AD9640. This maximum current occurs when every output bit

switches on every clock cycle, that is, a full-scale square wave at

the Nyquist frequency, fCLK/2. In practice, the DRVDD current

is established by the average number of output bits switching,

which is determined by the sample rate and the characteristics

of the analog input signal. Reducing the capacitive load

presented to the output drivers can minimize digital power

consumption. The data in Figure 20 was taken with the same

operating conditions as the Typical Performance Characteristics

with a 5 pF load on each output driver.

Figure 20. Power vs. Clock Frequency@ 30 MHz

By asserting the PDWN mode (either through the SPI port or

by asserting the PDWN pin high), the AD9640 is placed in

power-down mode. In this state, the ADC typically dissipates

TBD mW. During power-down, the output drivers are placed in

a high impedance state. Asserting the PDWN pin low returns

the AD9640 to its normal operational mode. This pin is both

1.8V and 3.3V tolerant.

Low power dissipation in power-down mode is achieved by

shutting down the reference, reference buffer, biasing networks,

and clock. Internal capacitors are discharged when entering

power-down mode and then must be recharged when returning

to normal operation. As a result, the wake-up time is related to

the time spent in power-down mode and shorter power-down

cycles result in proportionally shorter wake-up times. It takes

approximately TBD sec to fully discharge the internal reference

buffer decoupling capacitors and TBD ms to restore full

operation.

When using the SPI port interface, the user can place the ADC

in power-down or standby modes. Standby mode allows the

user to keep the internal reference circuitry powered when

faster wake-up times are required. See the SPI Register Map

Description section for more details.

DIGITAL OUTPUTS

The AD9640 output drivers can be configured to interface with

1.8 V to 3.3 V logic families by matching DRVDD to the digital

supply of the interfaced logic.

In CMOS output mode, the output drivers are sized to provide

sufficient output current to drive a wide variety of logic

families. However, large drive currents tend to cause current

glitches on the supplies that may affect converter performance.

Applications requiring the ADC to drive large capacitive loads

or large fan-outs may require external buffers or latches.

The output data format can be selected for either offset binary

or twos complement by setting the CLK/DFS pin when

operating in the external pin mode (see Table 3). As detailed in

the memory map register description section the data format

can be selected for either offset binary, twos complement, or

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