AD9640SLASHPCB datasheet(32/41 Pages) AD

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AD9640

Preliminary Technical Data

Rev. PrD | Page 32 of 41

SERIAL PORT INTERFACE (SPI)

The AD9640 serial port interface (SPI) allows the user to

configure the converter for specific functions or operations

through a structured register space provided inside the ADC.

This gives the user added flexibility and customization

depending on the application. Addresses are accessed via the

serial port and may be written to or read from via the port.

Memory is organized into bytes that can be further divided

down into fields, which are documented in the Memory Map

section. Detailed operational information can be found in the

Analog Devices user manual titled Interfacing to High Speed

ADCs via SPI at www.analog.com.

CONFIGURATION USING THE SPI

There are three pins that define the SPI of this ADC. They are

the SCLK/DFS, SDIO/DCS, and CSB pins (summarized inTable

x). The SCLK/DFS (serial clock) is used to synchronize the read

and write data presented from/to the ADC. The SDIO/DCS

(serial data input/output) is a dual purpose pin that allows data

to be sent and read from the internal ADC memory map

registers. The CSB (chip select bar) is an active low control that

enables or disables the read and write cycles.

Table xx. Serial Port Interface Pins

Function

SCLK

SCLK (Serial Clock) is the serial shift clock in. SCLK is

used to synchronize serial interface reads and writes.

SDIO

SDIO (Serial Data Input/Output) is a dual purpose pin.

The typical role for this pin is an input and output

depending on the instruction being sent and the

relative position in the timing frame.

CSB

CSB (Chip Select Bar) is active low controls that gates

the read and write cycles.

The falling edge of the CSB in conjunction with the rising edge

of the SCLK determines the start of the framing. An example of

the serial timing and its definitions can be found in Figure x

and Table x.

Other modes involving the CSB are available. The CSB can be

held low indefinitely which permanently enabling the device,

this is called streaming. The CSB may stall high between bytes

to allow for additional external timing. When CSB is tied high,

SPI functions are placed in a high impedance more. This mode

turns on any SPI pin secondary functions.

During an instruction phase a 16bit instruction is transmitted.

Data follows the instruction phase and it’s length is determined

by the W0 and W1 bits. All data is composed of 8bit words. The

first bit of each individual byte of serial data indicates whether a

read or write command is issued. This allows the serial data

input/output (SDIO) pin to change direction from an input to

an output.

In addition to word length, the instruction phase determines if

the serial frame is a read or write operation, allowing the serial

port to be used both to program the chip as well as read the

contents of the on-chip memory. If the instruction is a readback

operation, performing a readback causes the serial data input/

output (SDIO) pin to change direction from an input to an

output at the appropriate point in the serial frame.

Data may be sent in MSB or in LSB first mode. MSB first is

default on power up and may be changed via the configuration

“Interfacing to High Speed ADCs via SPI” at www.analog.com.

Table xx. SPI Timing Diagram Specifications

Spec

Name

Meaning

tDS

Setup time between data and rising edge of SCLK

tDH

Hold time between data and rising edge of SCLK

tCLK

Period of the clock

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHI

Minimum period that SCLK should be in a logic high

state

tLO

Minimum period that SCLK should be in a logic low

state

HARDWARE INTERFACE

The pins described in Table xError! Reference source not

found.

comprise the physical interface between the user’s

programming device and the serial port of the AD9640. All

serial pins are inputs, which should be tied to an external pull-

up or pull-down resistor (suggested value 10 kΩ).

The SPI interface is flexible enough to be controlled by either

FPGAs or mirocontrollers. This provides the user the ability use

an alternate method to program the ADC other than a

dedicated SPI controller.

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Since the

SCLK, CSB and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade the converter’s

performance. If the on board SPI Bus is utilized for other

devices it may be necessary to provide buffers between this bus

and the AD9640 in order to keep these signals from

transitioning at the converter inputs during critical sampling

periods.

Some pins serve a dual function when the SPI interface is not

being used. When the pins are strapped to AVDD or ground

during device power on, they are associated with a specific

function. The TBD section describes the strappable functions

supported on the AD9640.

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