AD9640SLASHPCB datasheet(39/41 Pages) AD

39 / 41 page

Preliminary Technical Data

AD9640

Rev. PrD | Page 39 of 41

APPLICATIONS

DESIGN GUIDELINES

When designing the AD9640 into a system, it is recommended

that, before starting design and layout, the designer become

familiar with these guidelines, which discuss the special circuit

connections and layout requirements required for certain pins.

Power and Ground Recommendations

When connecting power to the AD9640, it is recommended

that two separate 1.8 V supplies be used: one supply should be

used for analog (AVDD) and digital (DVDD) and a separate

supply for the digital outputs (DRVDD). The AVDD and

DVDD supplies, while derived from the same source, should be

isolated with a ferrite bead or filter choke and separate

decoupling capacitors. The user can employ several different

decoupling capacitors to cover both high and low frequencies.

These should be located close to the point of entry at the PC

board level and close to the part’s pins with minimal trace

length.

A single PC board ground plane should be sufficient when

using the AD9640. With proper decoupling and smart parti-

tioning of the PC board’s analog, digital, and clock sections,

optimum performance is easily achieved.

Exposed Paddle Thermal Heat Slug Recommendations

It is mandatory that the exposed paddle on the underside of the

ADC is connected to analog ground (AGND) to achieve the

best electrical and thermal performance of the AD9640. A

continuous exposed (no solder mask) copper plane on the PCB

should mate to the AD9640 exposed paddle, Pin 0. The copper

plane should have several vias to achieve the lowest possible

resistive thermal path for heat dissipation to flow through the

bottom of the PCB. These vias should be filled or plugged with

nonconductive epoxy.

To maximize the coverage and adhesion between the ADC and

PCB, overlay a silkscreen to partition the continuous plane on

the PCB into several uniform sections. This provides several tie

points between the two during the reflow process. Using one

continuous plane with no partitions only guarantees one tie

point between the ADC and PCB. See the evaluation board for a

PCB layout example. For detailed information on packaging

and the PCB layout of chip scale packages, see the AN-772

Application Note, “A Design and Manufacturing Guide for the

Lead Frame Chip Scale Package (LFCSP),” at www.analog.com.

CML

The CML pin should be decoupled to ground with a 0.1uF

capacitor, as shown in Figure 5.

RBIAS

The AD9640 requires the user to place a 10KΩ resistor between

the RBIAS pin and ground. This resister sets the master current

reference of the ADC core and should have at least a 1%

tolerance.

Reference Decoupling

The VREF pin should be externally decoupled to ground with a

low ESR 1.0uF capacitor in parallel with a 0.1uF ceramic low

ESR capacitor.

SPI Port

The SPI port should not be active during periods when the full

dynamic performance of the converter is required. Since the

SCLK, CSB and SDIO signals are typically asynchronous to the

ADC clock, noise from these signals can degrade the converter’s

performance. If the on board SPI Bus is utilized for other

devices it may be necessary to provide buffers between this bus

and the AD9640 in order to keep these signals from

transitioning at the converter inputs during critical sampling

periods.

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