AD9640SLASHPCB datasheet(21/41 Pages) AD

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Preliminary Technical Data

AD9640

Rev. PrD | Page 21 of 41

Figure 14. Transformer Coupled Differential Clock(up to 150MSPS)

CLOCK

INPUT

0.1µF

~CLK

CLK

AD9510/1/2/3/4/5

CMOS DRIVER

ADC

AD9640

50kΩ

OPTIONAL

100Ω

1kΩ

VCC

If a low jitter clock source is not available, another option is to

ac-couple a differential PECL signal to the sample clock input

pins as shown in Figure 15. The AD9510/AD9511/AD9512/

AD9513/AD9514/AD9515 family of clock drivers offers

excellent jitter performance.

CLOCK

INPUT

100kΩ

0.1µF

~CLK

CLK

240kΩ

50kΩ

~ CLOCK

INPUT

AD9510/1/2/3/4/5

PECL DRIVER

ADC

AD9640

Figure 15. Differential PECL Sample Clock (up to 150MSPS)

A third option is to ac-couple a differential LVDS signal to the

sample clock input pins as shown in Figure 16. The

AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515 family of

clock drivers offers excellent jitter performance.

Figure 16 Differential LVDS Sample Clock (up to 150MSPS)

In some applications it may acceptable to drive the sample clock

inputs with a single ended CMOS signal. In such applications,

CLK+ should be directly driven from a CMOS gate, while the

CLK- pin should be bypassed to ground with a 0.1uF capacitor

in parallel with a 39 kΩ resistor (see Figure 17). CLK+ may be

directly driven from a CMOS gate. Although the CLK+ input

circuit supply is AVDD (1.8 V), this input is designed to

withstand input voltages up to 3.6V, making the selection of the

drive logic voltage very flexible.

Figure 17. Single-ended 1.8V CMOS Sample Clock (up to 150MSPS)

Figure 18 Single-ended 3.3V CMOS Sample Clock (up to 150MSPS)

Input Clock Divider

The AD9640 contains an input clock divider with the ability to

divide the input clock by integer values between 1 and 8. If a

divide ratio other than 1 is selected the duty cycle stabilizer will

be automatically enabled.

The AD9640 clock divider can be synchronized using the

external SYNC input. Register 0x100 bits bits 1 and 2 allow the

clock divider to be re-synchronized on every SYNC signal or

only on the first SYNC signal after the register is written. A

valid SYNC causes the clock divider to reset to its initial state.

This synchronization feature allows multiple parts to have their

clock dividers aligned to guarantee simultaneous input

sampling.

CLOCK

INPUT

100kΩ

0.1µF

~CLK

CLK

50kΩ

~ CLOCK

INPUT

AD9510/1/2/3/4/5

LVDS DRIVER

ADC

AD9640

Clock Duty Cycle

Typical high speed ADCs use both clock edges to generate a

variety of internal timing signals, and as a result may be

sensitive to clock duty cycle. Commonly, a ±5% tolerance is

required on the clock duty cycle to maintain dynamic

performance

characteristics. The AD9640 contains a duty cycle stabilizer

(DCS) that retimes the nonsampling, or falling, edge, providing

an internal clock signal with a nominal 50% duty cycle. This

allows the user to provide a wide range of clock input duty

cycles without affecting the performance of the AD9640. Noise

and distortion performance are nearly flat for a wide range of

duty cycles with the DCS on, as shown in Figure x.

The duty cycle stabilizer uses a delay-locked loop (DLL) to

create the nonsampling edge. As a result, any changes to the

sampling frequency require approximately TBD clock cycles to

allow the DLL to acquire and lock to the new rate.

CLOCK

INPUT

0.1µF

~CLK

CLK

39kΩ

AD9510/1/2/3/4/5

CMOS DRIVER

ADC

AD9640

VCC

50kΩ

OPTIONAL

100Ω

1kΩ

Jitter Considerations

High speed, high resolution ADCs are sensitive to the quality of

the clock input. The degradation in SNR at a given input

frequency (fINPUT) due to jitter (tJ) can be calculated by:

[

]

INPUT

−

log

SNR

In the equation, the rms aperture jitter represents the root-

mean square of all jitter sources, which include the clock input,

analog input signal, and ADC aperture jitter specification. IF

undersampling applications are particularly sensitive to jitter, as

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