AD9640SLASHPCB datasheet(19/41 Pages) AD

19 / 41 page

Preliminary Technical Data

AD9640

Rev. PrD | Page 19 of 41

Figure 8 details a typical single-ended input configuration.

2V p-p

49.9Ω

0.1µF

10µF

0.1µF

AVDD

1kΩ

VIN+

VIN–

ADC

AD9640

AVDD

Figure 8. Single-Ended Input Configuration

Table 2. Reference Configuration Summary

Selected Mode

SENSE Voltage

Resulting VREF (V)

Resulting Differential

Span (V p-p)

External Reference

AVDD

N/A

2 × External Reference

Internal Fixed Reference

VREF

0.5

1.0

Programmable Reference

0.2 V to VREF

⎟

⎠

⎞

⎜

⎝

⎛ +

(See Figure 10)

2 × VREF

Internal Fixed Reference

AGND to 0.2 V

1.0

2.0

VOLTAGE REFERENCE

A stable and accurate voltage reference is built into the AD9640.

The input range can be adjusted by varying the reference

voltage applied to the AD9640, using either the internal

reference or an externally applied reference voltage. The input

span of the ADC tracks reference voltage changes linearly. The

various reference modes are summarized in the next few

sections. The Reference Decoupling section describes the best

practices PCB layout of the reference.

Internal Reference Connection

A comparator within the AD9640 detects the potential at the

SENSE pin and configures the reference into four possible

states, which are summarized in Table x. If SENSE is grounded,

the reference amplifier switch is connected to the internal

resistor divider (see Figure 9), setting VREF to 1 V. Connecting

the SENSE pin to VREF switches the reference amplifier output

to the SENSE pin, completing the loop and providing a 0.5 V

reference output. If a resistor divider is connected external to

the chip as shown in Figure 10, the switch again sets to the

SENSE pin. This puts the reference amplifier in a noninverting

mode with the VREF output defined as

⎟

⎠

⎞

⎜

⎝

⎛ +

VREF

The input range of the ADC always equals twice the voltage at

the reference pin for either an internal or an external reference.

0.1uF

VREF

SENSE

0.5V

AD9640

VIN-A/VIN-B

VIN+A/VIN+B

SELECT

LOGIC

ADC

CORE

1.0uF

Figure 9. Internal Reference Configuration

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