AD9640SLASHPCB datasheet(33/41 Pages) AD

33 / 41 page

Preliminary Technical Data

AD9640

Rev. PrD | Page 33 of 41

CONFIGURATION WITHOUT THE SPI

In applications that do not interface to the SPI control registers,

the SDIO/DCS, SCLK/DFS, MON SDO/OEB, and MON

SCLK/PDWN pins serve as stand alone CMOS compatible

control pins. When the device is powered up, it is assumed that

the user intends to use the pins as static control lines for the

duty cycle stabilizer, output data format, output enable, and

power down feature control. In this mode the CSB chip select

should be connected to AVDD, which will disable the serial

port interface.

Table 5. Mode Selection

External

Voltage

Configuration

AVDD (default)

Duty Cycle Stabilizer Enabled

SDIO/DCS

AGND

Duty Cycle Stabilizer Disabled

AVDD

Twos Complement Enabled

SCLK/DFS

AGND (default)

Offset Binary Enabled

AVDD

Outputs in High Impedance

MON SDO/

OEB

AGND (default)

Outputs Enabled

AVDD

Chip in PowerDown/Standby

MON SCLK/

PDWN

AGND (default)

Normal Operation

MEMORY MAP

Reading the Memory Map Table

Each row in the memory map table has eight bit locations. The

memory map is roughly divided into four sections: chip

configuration and ID register map (Address 0x00 to Address

0x05), ADC setup, control and test (Addresses 0x08 to Address

0x25), transfer register map (Address 0xFF), and digital feature

control (Address 0x100 to Address 0x11B).

Starting from the right hand column, the memory map register

in Table x documents the default hex value for each hex address

shown. The column with the heading Bit 7 (MSB) is the start of

the default hex value given. For example, hex address 0x18,

reference select, has a hex default value of 0xC0. This means Bit

7 = 1, Bit 6 = 1, and the remaining bits are zeros. This setting is

the default reference selection setting. The default value uses a

2.0V peak to peak reference. For more information on this

function and others consult “Interfacing to High Speed ADCs via

SPI” at www.analog.com.

Open Locations

All address and bit locations that are not included in Table x are

currently not supported for this device. Unused bits of a valid

address location should be written with 0s. Writing to these

locations is required only when part of an address location is

open (for example, Address 0x18). If the entire address location

is open (for example, Address 0x13), then this address location

should not be written.

Default Values

Coming out of reset, critical registers are loaded with default

values. The default values for the registers are given in the

Memory Map Table.

Logic Levels

An explanation of various registers follows: “bit is set” is

synonymous with “bit is set to Logic 1” or “writing Logic 1 for

the bit.” Similarly “clear a bit” is synonymous with “bit is set to

Logic 0” or “writing Logic 0 for the bit.”

Transfer Register Map

Addresses 0x08 to 0x18 are shadowed. Writes to these

addresses do not affect the part operation until a transfer

command is issued by writing a 0x01 to address 0xFF setting

the transfer bit. This allows these registers to be updated

internally simultaneously when the transfer bit is set. The

internal update takes place when the transfer bit is set and the

bit autoclears.

Channel Specific Registers

Some channel setup functions such as the signal monitor

thresholds can be programmed differently for each channel. In

these cases channel address locations are internally duplicated

for each channel. These registers are designated in the

‘Parameter Name’ column of Table x as (local) registers. These

local registers can be accessed by setting the appropriate

Channel A or Channel B bits in register 0x05. If both bits are

set the subsequent write will affect both channels’ registers. In a

read cycle only Channel A or Channel B should be set to read

one of the two registers. If both bits are set during a SPI read

cycle the part returns the value for channel A. Registers

designated as (global) in the ‘Parameter Name’ column of Table

x affect the entire part or the channel features where

independent settings are not allowed between the channels.

The settings in register 0x05 do not affect the global registers.

SPI ACCESSIBLE FEATURES

A brief description of all features accessible via the SPI follows.

They are described in great detail in the Analog Devices user

manual titled Interfacing to High Speed ADCs via SPI at

www.analog.com.

Modes: Allows the user to set either power-down or standby

mode.

Clock:

Allows the user to access the DCS via the SPI.

Offset:

Allows the user to digitally adjust the converter offset.

Test IO: Allows the user to set test modes to have known data

on output bits.

Output Mode: Allows the user to setup outputs.

Output phase: Allows user to set the output clock polarity.

Output Delay: Allows user to vary the strength of the output

drivers.

Vref:

Allows the user to set the reference voltage.

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