Datenblatt-Suchmaschine für elektronische Bauteile
  German  ▼
ALLDATASHEETDE.COM

X  

AD9640/PCB Datenblatt(PDF) 23 Page - Analog Devices

Teilenummer AD9640/PCB
Bauteilbeschribung  14-Bit, 80/105/125/150 MSPS, 1.8 V Dual Analog-to-Digital Converter
PDF  41 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9640/PCB Datenblatt(HTML) 23 Page - Analog Devices

Back Button AD9640/PCB Datasheet HTML 19Page - Analog Devices AD9640/PCB Datasheet HTML 20Page - Analog Devices AD9640/PCB Datasheet HTML 21Page - Analog Devices AD9640/PCB Datasheet HTML 22Page - Analog Devices AD9640/PCB Datasheet HTML 23Page - Analog Devices AD9640/PCB Datasheet HTML 24Page - Analog Devices AD9640/PCB Datasheet HTML 25Page - Analog Devices AD9640/PCB Datasheet HTML 26Page - Analog Devices AD9640/PCB Datasheet HTML 27Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 23 / 41 page
background image
Preliminary Technical Data
AD9640
Rev. PrD | Page 23 of 41
Gray code when using the SPI control.
Table 3. CLK/DFS Mode Selection (external pin mode)
Voltage at pin
SCLK/DFS
SDIO/DCS
AGND (default)
Binary
DCS Disabled
AVDD
Twos Complement
DCS Enabled
Digital Output Enable Function (OEB)
The AD9640 has a flexible three-state ability for the digital
output pins. The three-state mode can be enabled using the
OEB pin or through the SPI interface. If the OEB pin is low, the
output data drivers are enabled. If the OEB pin is high, the
output data drivers are placed in a high impedance state. It is
not intended for rapid access to the data bus. Note that OEB is
referenced to the digital supplies (DRVDD) and should not
exceed that supply voltage.
Figure 21. OR Relation to Input Voltage and Output Data
TIMING
The AD9640 provides latched data with a pipeline delay of
twelve clock cycles. Data outputs are available one propagation
delay (tPD) after the rising edge of the clock signal.
When using the SPI interface each channel’s data and fast detect
outputs can be independently three-stated by using the Output
Enable Bar bit in register 0x14.
The length of the output data lines and loads placed on them
should be minimized to reduce transients within the AD9640.
These transients can degrade the converter’s dynamic performance.
The AD9640 also provides data clock output (DCO) intended for
capturing the data in an external register. The data outputs are
valid on the rising edge of DCO. See Figure x for a graphical
timing description.
The lowest typical conversion rate of the AD9640 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can
degrade.
Table 4. Output Data Format
Input (V)
Condition (V)
Binary Output Mode
Twos Complement Mode
OR
VIN+ – VIN–
< –VREF – 0.5 LSB
00 0000 0000 0000
10 0000 0000 0000
1
VIN+ – VIN–
= –VREF
00 0000 0000 0000
10 0000 0000 0000
0
VIN+ – VIN–
= 0
10 0000 0000 0000
00 0000 0000 0000
0
VIN+ – VIN–
= +VREF – 1.0 LSB
11 1111 1111 1111
01 1111 1111 1111
0
VIN+ – VIN–
> +VREF – 0.5 LSB
11 1111 1111 1111
01 1111 1111 1111
1



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41


Datenblatt Download

Go To PDF Page


Link URL



War ALLDATASHEET hilfreich?  [ DONATE ] 

Über Alldatasheet   |   Werbung   |   Kontakt   |   Privatsphäre und Datenschutz   |   Link zum Datenblatt    |   Linktausch   |   Hersteller
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com